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    Memory controller and method of operating the same
    1.
    发明授权
    Memory controller and method of operating the same 有权

    公开(公告)号：US11481272B2

    公开(公告)日：2022-10-25

    申请号：US16945068

    申请日：2020-07-31

    Applicant: SK hynix Inc.

    Inventor： Ki Young Kim

    IPC: G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/07 ,  G06F12/02 ,  G06F12/0882 ,  G06F11/30

    Abstract: The present technology relates to an electronic device. A memory controller controls a memory device such that a life of the memory device is increased. The memory controller that controls the memory device includes a flash translation layer configured to generate a device health descriptor based on device information received from the memory device, and a bad block controller configured to generate a bad block table based on bad block information received from the memory device, and generate recycling information for recycling pages in bad blocks recorded in the bad block table based on the device health descriptor.

    Memory controller and operating method thereof
    3.
    发明授权
    Memory controller and operating method thereof 有权

    公开(公告)号：US11995352B2

    公开(公告)日：2024-05-28

    申请号：US17746304

    申请日：2022-05-17

    Applicant: SK hynix Inc.

    Inventor： Ki Young Kim

    IPC: G06F3/06 ,  H04L67/1097

    CPC classification number: G06F3/0659 ,  G06F3/0607 ,  G06F3/0658 ,  G06F3/0679 ,  H04L67/1097

    Abstract: The embodiments of the present disclosure relate to a memory controller and operating method thereof. According to embodiments of the present disclosure, the memory controller may include a memory configured to store an activation candidate list including one or more nodes each indicating a logical address range that satisfies a preset activation candidate condition, and a processor configured to determine a target node based on activation parameters of logical address ranges indicated by respective nodes included in the activation candidate list, determine, as activation logical address ranges, one or more logical address ranges from the activation candidate list based on the target node, and transmit information indicating the activation logical address range to a host.

    Electronic device and method of operating the same
    6.
    发明授权
    Electronic device and method of operating the same 有权

    公开(公告)号：US11901907B2

    公开(公告)日：2024-02-13

    申请号：US17521603

    申请日：2021-11-08

    Applicant: SK hynix Inc.

    Inventor： Sang Eun Je ,  Ki Young Kim

    IPC: H03M1/00 ,  G11C13/00 ,  G06N3/065

    CPC classification number: H03M1/002 ,  G06N3/065 ,  G11C13/003

    Abstract: An electronic device includes analog-to-digital converters each configured to receive an analog input signal and output a digital output signal corresponding to the analog input signal, an analog input signal generator configured to generate analog input signals provided to each analog-to-digital converter based on input voltages and weight data, an input signal distribution information generator configured to generate input signal distribution information indicating a distribution of the analog input signals for each of the analog-to-digital converters, an analog-to-digital converter group classifier configured to classify the analog-to-digital converters into a plurality of first analog-to-digital converter groups based on the input signal distribution information, and an analog-to-digital converter input range optimizer configured to determine an input range of each first analog-to-digital converter group based on the input signal distribution information, and each analog-to-digital converter is configured to operate according to an input range of a corresponding first analog-to-digital converter groups.

    Data processing apparatus and operating method thereof
    7.
    发明授权
    Data processing apparatus and operating method thereof 有权

    公开(公告)号：US11449449B2

    公开(公告)日：2022-09-20

    申请号：US16997256

    申请日：2020-08-19

    Applicant: SK hynix Inc.

    Inventor： Ki Young Kim

    IPC: G06F13/372 ,  G06F13/374 ,  G06F1/14 ,  G06F9/38 ,  G06F9/48

    Abstract: A data processing apparatus includes a master device configured to transmit commands for destinations, a slave device including a plurality of command processing regions respectively corresponding to the destinations, and a controller configured to relay communication between the master device and the slave device. The controller assigns time stamp value to the commands as an initial value when the commands was received by the controller and increment the time stamp value every command arbitration cycle, selects a command having a largest time stamp value among the commands in a tournament manner by comparing commands having different destinations every command arbitration cycle, stores a command selection history of each comparison of commands, selects the command based on a command selection history corresponding to the compared commands when respective time stamp values of the compared commands are the same or substantially the same as each other.

    Apparatus and method for transmitting, based on assignment of block to HPB region, metadata generated by a non-volatile memory system
    9.
    发明授权
    Apparatus and method for transmitting, based on assignment of block to HPB region, metadata generated by a non-volatile memory system 有权

    公开(公告)号：US11507501B2

    公开(公告)日：2022-11-22

    申请号：US17384543

    申请日：2021-07-23

    Applicant: SK hynix Inc.

    Inventor： Ki Young Kim

    IPC: G06F12/02

    Abstract: A memory system includes a memory device including memory blocks, each memory block including a memory cell capable of storing a multi-bit data item. The memory device includes a write booster region including at least one memory block among the plurality of memory blocks, the at least one memory block including a memory cell storing a single-bit data item. A controller is configured to assign a memory block in the write booster region to a host performance booster (HPB) region when the memory block is closed and transmit to a host an indication that the memory block is assigned to the HPB region.

    Semiconductor package including a semiconductor chip having a redistribution layer
    10.
    发明授权
    Semiconductor package including a semiconductor chip having a redistribution layer 有权

    公开(公告)号：US11217544B2

    公开(公告)日：2022-01-04

    申请号：US17002422

    申请日：2020-08-25

    Applicant: SK hynix Inc.

    Inventor： Jong Hyun Kim ,  Seung Hwan Kim ,  Hyun Chul Seo ,  Ki Young Kim

    IPC: H01L23/00 ,  H01L25/065 ,  H01L23/528 ,  H01L23/532

    Abstract: A semiconductor package includes: a package substrate; a first semiconductor chip disposed over the package substrate and having a center region and an edge region; and a package redistribution layer disposed over the first semiconductor chip, wherein the first semiconductor chip comprises: a lower structure; a redistribution conductive layer disposed over the lower structure and electrically connected to the lower structure, the redistribution conductive layer including a redistribution pad disposed in the center region; and a protective layer covering the lower structure and the redistribution conductive layer, and having an opening exposing the redistribution pad, wherein the package redistribution layer comprises: a package redistribution conductive layer connected to the redistribution pad and extending to the edge region, the package redistribution conductive layer including a package redistribution pad disposed in the edge region, and, wherein, in the edge region, the redistribution conductive layer is omitted.

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