公开(公告)号：US09397757B2

公开(公告)日：2016-07-19

申请号：US14318529

申请日：2014-06-27

Applicant: SK HYNIX INC.

Inventor： In Chul Hwang ,  Il Hwan Cho ,  Ki Young Kim ,  Kyoung Mo Yang ,  Jae Joon Ahn ,  Chong Ho Cho

IPC: H04B10/80 ,  H04B10/40 ,  G02B6/42 ,  H05K1/18

CPC classification number: H04B10/801 ,  G02B6/42 ,  H01L2224/16145 ,  H01L2224/16225 ,  H04B10/40 ,  H05K1/181 ,  H05K2201/10121 ,  H05K2201/10515 ,  Y02P70/611

Abstract: A semiconductor package includes a package substrate, a first semiconductor substrate and a second semiconductor substrate stacked on the package substrate, and an optical transceiver that generates and receives an optical signal travelling between the package substrate and the second semiconductor substrate using an infrared (IR) ray that passes through the first semiconductor substrate.

Abstract translation: 半导体封装包括封装衬底，堆叠在封装衬底上的第一半导体衬底和第二半导体衬底，以及使用红外线（IR）产生并接收在封装衬底和第二半导体衬底之间行进的光信号的光收发器， 射线穿过第一半导体衬底。

公开(公告)号：US09668344B2

公开(公告)日：2017-05-30

申请号：US14878891

申请日：2015-10-08

Applicant: SK hynix Inc.

Inventor： Won Duck Jung ,  Jong Ho Lee ,  Joo Hyun Kang ,  Chong Ho Cho ,  In Chul Hwang

IPC: H05K7/00 ,  H05K7/12 ,  H05K1/11 ,  H01L27/115 ,  H05K1/14 ,  H05K3/32

CPC classification number: H05K1/111 ,  H01L21/563 ,  H01L23/49811 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L27/115 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/11334 ,  H01L2224/13011 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1601 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81897 ,  H01L2224/8192 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/3511 ,  H05K1/145 ,  H05K3/32 ,  H05K3/325 ,  H05K2201/09209 ,  H05K2201/10159 ,  H05K2201/10287 ,  H05K2201/10613 ,  H05K2201/10757 ,  H05K2201/1078 ,  H05K2201/10977 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/45099

Abstract: A semiconductor package may include a first substrate including a first connection portion disposed on a surface of the first substrate and a second substrate including a second connection portion disposed on a surface of the second substrate. The second substrate may be disposed over the first substrate and the second connection portion facing the first connection portion. A first connection loop portion may be provided to include an end connected to the first connection portion. A second connection loop portion may be provided to include one end connected to the second connection portion and the other end combined with the first connection loop portion.

公开(公告)号：US09093441B2

公开(公告)日：2015-07-28

申请号：US13846713

申请日：2013-03-18

Applicant: SK hynix Inc.

Inventor： Ji Eun Kim ,  Cheol Ho Joh ,  Hee Min Shin ,  Kyu Won Lee ,  Chong Ho Cho

IPC: H01L25/04 ,  H01L25/065 ,  H01L25/075 ,  H01L23/498 ,  H01L21/683 ,  H01L25/00 ,  H01L29/06 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L21/6836 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L24/92 ,  H01L25/043 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/0756 ,  H01L25/50 ,  H01L29/0657 ,  H01L2221/68327 ,  H01L2224/04042 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/49174 ,  H01L2224/73265 ,  H01L2224/78346 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10158 ,  H01L2924/1531 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The semiconductor package includes an upper semiconductor chip stacked on a package substrate and a support layer or a lower semiconductor chip disposed between the upper semiconductor chip and the package substrate. The upper semiconductor chip includes a protrusion downwardly extending from an edge thereof. The protrusion of the upper semiconductor chip is combined with a sidewall of the support layer or the lower semiconductor chip. Related methods are also provided.

Abstract translation: 半导体封装包括堆叠在封装衬底上的上半导体芯片和设置在上半导体芯片和封装衬底之间的支撑层或下半导体芯片。 上半导体芯片包括从其边缘向下延伸的突起。 上半导体芯片的突起与支撑层或下半导体芯片的侧壁组合。 还提供了相关方法。

公开(公告)号：US08951810B2

公开(公告)日：2015-02-10

申请号：US13719082

申请日：2012-12-18

Applicant: SK hynix Inc.

Inventor： Kyu Won Lee ,  Cheol Ho Joh ,  Ji Eun Kim ,  Hee Min Shin ,  Chong Ho Cho

IPC: H01L21/00 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L21/4846 ,  H01L21/4867 ,  H01L23/3178 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/02311 ,  H01L2224/02317 ,  H01L2224/02375 ,  H01L2224/0332 ,  H01L2224/03515 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05554 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Methods of forming an interconnection line pattern using a screen printing technique. The method includes preparing a substrate having unevenness, aligning a stencil mask on the substrate, and printing a paste including materials for forming the interconnection line pattern on a convex portion of the unevenness formed on the substrate.

Abstract translation: 使用丝网印刷技术形成互连线图案的方法。 该方法包括制备具有凹凸的基板，使基板上的模板掩模对准，以及在形成在基板上的凹凸的凸部上印刷包括用于形成互连线图案的材料的浆料。