公开(公告)号：US20250014999A1

公开(公告)日：2025-01-09

申请号：US18894714

申请日：2024-09-24

Applicant: SK hynix Inc.

Inventor： Won Duck JUNG

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/498 ,  H01L23/552 ,  H01L25/065

Abstract: A semiconductor package is configured to include a package substrate, a semiconductor chip disposed on the package substrate, and bonding wires. The package substrate includes a first column of bond fingers disposed in a first layer and a second column of bond fingers disposed in a second layer. The semiconductor chip includes a first column of chip pads arrayed in a first column and a second column of chip pads arrayed in a second column adjacent to the first column. The first column of chip pads are connected to the first column of bond fingers, respectively, through first bonding wires, and the second column of chip pads are connected to the second column of bond fingers, respectively, through second bonding wires.

公开(公告)号：US20170309600A1

公开(公告)日：2017-10-26

申请号：US15280404

申请日：2016-09-29

Applicant: SK hynix Inc.

Inventor： Won Duck JUNG ,  Sung Ho HYUN ,  Ju Il EOM

IPC: H01L25/07 ,  H01L23/498 ,  H01L23/535 ,  H01L23/31

CPC classification number: H01L25/071 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/535 ,  H01L25/0655 ,  H01L25/074 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A planar dual die package includes a package substrate and first and second semiconductor dice disposed side by side on a first surface of the package substrate. Outer connectors are disposed on a second surface of the package substrate, and the second surface of the package substrate includes a command/address ball region and a data ball region. Each of the first and second semiconductor dice includes die pads disposed in a command/address pad region corresponding to the command/address ball region and in a data pad region corresponding to the data ball region. Each of the first and second semiconductor dice are disposed on the package substrate so that a first direction from the command/address ball region toward the data ball region coincides with a second direction from the command/address pad region toward the data pad region.

公开(公告)号：US20190139940A1

公开(公告)日：2019-05-09

申请号：US16237292

申请日：2018-12-31

Applicant: SK hynix Inc.

Inventor： Won Duck JUNG ,  Sung Ho HYUN ,  Ju Il EOM

IPC: H01L25/07 ,  H01L23/535 ,  H01L23/498 ,  H01L23/31

Abstract: A planar dual die package includes a package substrate and first and second semiconductor dice disposed side by side on a first surface of the package substrate. Outer connectors are disposed on a second surface of the package substrate, and the second surface of the package substrate includes a command/address ball region and a data ball region. Each of the first and second semiconductor dice includes die pads disposed in a command/address pad region corresponding to the command/address ball region and in a data pad region corresponding to the data ball region. Each of the first and second semiconductor dice are disposed on the package substrate so that a first direction from the command/address ball region toward the data ball region coincides with a second direction from the command/address pad region toward the data pad region.

公开(公告)号：US20160316559A1

公开(公告)日：2016-10-27

申请号：US14878891

申请日：2015-10-08

Applicant: SK hynix Inc.

Inventor： Won Duck JUNG ,  Jong Ho LEE ,  Joo Hyun KANG ,  Chong Ho CHO ,  In Chul HWANG

IPC: H05K1/11

CPC classification number: H05K1/111 ,  H01L21/563 ,  H01L23/49811 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L27/115 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/11334 ,  H01L2224/13011 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1601 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81897 ,  H01L2224/8192 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/3511 ,  H05K1/145 ,  H05K3/32 ,  H05K3/325 ,  H05K2201/09209 ,  H05K2201/10159 ,  H05K2201/10287 ,  H05K2201/10613 ,  H05K2201/10757 ,  H05K2201/1078 ,  H05K2201/10977 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/45099

Abstract: A semiconductor package may include a first substrate including a first connection portion disposed on a surface of the first substrate and a second substrate including a second connection portion disposed on a surface of the second substrate. The second substrate may be disposed over the first substrate and the second connection portion facing the first connection portion. A first connection loop portion may be provided to include an end connected to the first connection portion. A second connection loop portion may be provided to include one end connected to the second connection portion and the other end combined with the first connection loop portion.

Abstract translation: 半导体封装可以包括第一衬底，其包括设置在第一衬底的表面上的第一连接部分和包括设置在第二衬底的表面上的第二连接部分的第二衬底。 第二基板可以设置在第一基板上，第二连接部分面向第一连接部分。 可以提供第一连接环部分以包括连接到第一连接部分的端部。 可以提供第二连接环部分以包括连接到第二连接部分的一端和与第一连接环部分组合的另一端。

公开(公告)号：US20210118800A1

公开(公告)日：2021-04-22

申请号：US16863559

申请日：2020-04-30

Applicant: SK hynix Inc.

Inventor： Won Duck JUNG

IPC: H01L23/528 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package is configured to include a package substrate, a semiconductor chip disposed on the package substrate, and bonding wires. The package substrate includes a first column of bond fingers disposed in a first layer and a second column of bond fingers disposed in a second layer. The semiconductor chip includes a first column of chip pads arrayed in a first column and a second column of chip pads arrayed in a second column adjacent to the first column. The first column of chip pads are connected to the first column of bond fingers, respectively, through first bonding wires, and the second column of chip pads are connected to the second column of bond fingers, respectively, through second bonding wires.

公开(公告)号：US20190081009A1

公开(公告)日：2019-03-14

申请号：US16186305

申请日：2018-11-09

Applicant: SK hynix Inc.

Inventor： Won Duck JUNG ,  Sang Joon LIM ,  Sung Mook LIM

IPC: H01L23/552 ,  H01L23/482 ,  H01L23/00

Abstract: Disclosed is a semiconductor package. The semiconductor package may include a substrate a semiconductor chip mounted over a surface of the substrate such that an active surface of the semiconductor chip faces the surface of the substrate. The semiconductor chip and substrate may be configured for shielding or scattering electromagnetic waves.

公开(公告)号：US20220328412A1

公开(公告)日：2022-10-13

申请号：US17844337

申请日：2022-06-20

Applicant: SK hynix Inc.

Inventor： Won Duck JUNG

IPC: H01L23/528 ,  H01L25/065 ,  H01L23/00 ,  H01L23/552

Abstract: A semiconductor package is configured to include a package substrate, a semiconductor chip disposed on the package substrate, and bonding wires. The package substrate includes a first column of bond fingers disposed in a first layer and a second column of bond fingers disposed in a second layer. The semiconductor chip includes a first column of chip pads arrayed in a first column and a second column of chip pads arrayed in a second column adjacent to the first column. The first column of chip pads are connected to the first column of bond fingers, respectively, through first bonding wires, and the second column of chip pads are connected to the second column of bond fingers, respectively, through second bonding wires.

公开(公告)号：US20190393164A1

公开(公告)日：2019-12-26

申请号：US16236058

申请日：2018-12-28

Applicant: SK hynix Inc.

Inventor： Sung Mook LIM ,  Hye Won KIM ,  Won Duck JUNG

IPC: H01L23/552 ,  H01L23/66 ,  H01L23/522 ,  H01L23/00

Abstract: A package substrate includes a core layer including a first surface and a second surface, which are opposite to each other. The package substrate also includes a power plane interconnection layer disposed on the first surface of the core layer and a ground plane interconnection layer disposed on the second surface of the core layer. The package substrate additionally includes an electromagnetic (EM) bandgap structure disposed in the core layer and electrically coupled between the power plane interconnection layer and the ground plane interconnection layer. The EM bandgap structure includes an EM bandgap via protruding from a portion of the power plane interconnection layer toward the ground plane interconnection layer. The EM bandgap structure further includes an EM bandgap cylindrical structure extending from a portion of the ground plane interconnection layer toward the power plane interconnection layer and surrounding a side surface of the EM bandgap via.

公开(公告)号：US20160254251A1

公开(公告)日：2016-09-01

申请号：US14850385

申请日：2015-09-10

Applicant: SK hynix Inc.

Inventor： Han Jun BAE ,  Won Duck JUNG

IPC: H01L25/065

CPC classification number: H01L29/0657 ,  H01L23/145 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/4985 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/10158 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012

Abstract: A semiconductor device includes a substrate, an elastic buffer layer disposed on a surface of the substrate, wiring patterns disposed on a first surface of the elastic buffer layer, and a semiconductor chip disposed on a second surface of the elastic buffer layer facing away from the first surface of the elastic buffer layer. The semiconductor chip includes trenches formed on a surface facing the elastic buffer layer. Interconnection members are disposed to electrically connect the elastic buffer layer to the substrate. Each of the interconnection members has one end electrically connected to one of the wiring patterns and the other end electrically connected to the substrate.

Abstract translation: 半导体器件包括衬底，设置在衬底的表面上的弹性缓冲层，布置在弹性缓冲层的第一表面上的布线图案，以及布置在弹性缓冲层的背离弹性缓冲层的第二表面上的半导体芯片 弹性缓冲层的第一表面。 半导体芯片包括形成在面向弹性缓冲层的表面上的沟槽。 互连构件被设置为将弹性缓冲层电连接到衬底。 每个互连构件的一端电连接到一个布线图案，另一端电连接到基板。

公开(公告)号：US20210242176A1

公开(公告)日：2021-08-05

申请号：US16934555

申请日：2020-07-21

Applicant: SK hynix Inc.

Inventor： Won Duck JUNG

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a lower chip and an upper chip stacked on the lower chip. The lower chip includes lower chip pads arrayed in a plurality of lower columns on a top surface of the lower chip, wire bonding pads disposed on the top surface of the lower chip to be laterally spaced apart from the lower chip pads, and traces disposed on the top surface of the lower chip to electrically connect the lower chip pads to the wire bonding pads. The upper chip includes upper chip pads arrayed in a plurality of upper columns on a top surface of the upper chip and bumps disposed on the upper chip pads to contact the traces. The upper chip is stacked on the lower chip such that the top surface of the upper chip faces the top surface of the lower chip.