公开(公告)号：US20190080999A1

公开(公告)日：2019-03-14

申请号：US15982441

申请日：2018-05-17

Applicant: SK hynix Inc.

Inventor： Juil EOM ,  Sang Joon LIM ,  Bok Kyu CHOI

IPC: H01L23/522 ,  H05K1/02 ,  H01L23/64 ,  H05K1/16

Abstract: A package substrate may include a first total signal path having a first parasitic capacitance value and a second total signal path having a second parasitic capacitance value different from the first parasitic capacitance value. The package substrate may include a first capacitance adjustment pattern disposed within the package substrate and configured to reduce the difference between the first and second parasitic capacitance values.

公开(公告)号：US20180138150A1

公开(公告)日：2018-05-17

申请号：US15443509

申请日：2017-02-27

Applicant: SK hynix Inc.

Inventor： Ju Il EOM ,  Jae Hoon LEE ,  Sang Joon LIM

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/06137 ,  H01L2224/06177 ,  H01L2224/0912 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/14136 ,  H01L2224/16145 ,  H01L2224/17104 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/06135 ,  H01L2224/06136

Abstract: A semiconductor package may include a first semiconductor chip having first bonding pads on a first active surface. The semiconductor package may include a second semiconductor chip having second bonding pads which are arranged on a second active surface. The first and second semiconductor chips are stacked such that the first and second active surfaces face each other.

公开(公告)号：US20140176262A1

公开(公告)日：2014-06-26

申请号：US13901297

申请日：2013-05-23

Applicant: SK hynix Inc.

Inventor： Byung Jun BANG ,  Sang Joon LIM ,  Ju Il EOM ,  Bok Kyu CHOI ,  Jin Hwan SONG

IPC: H01P1/203

CPC classification number: H01P1/2039 ,  H01L2924/0002 ,  H01P1/203 ,  H05K1/0236 ,  H05K1/16 ,  H05K2201/09236 ,  H05K2201/09354 ,  H05K2201/09781 ,  H01L2924/00

Abstract: According to one embodiment, a semiconductor package includes a band stop filter, which includes: a transmission line pattern arranged on a package substrate; and a conductive stub pattern arranged along the transmission line pattern in a state of being separated from the transmission line pattern.

Abstract translation: 根据一个实施例，半导体封装包括带阻滤波器，其包括：布置在封装衬底上的传输线图案; 以及在与传输线图案分离的状态下沿着传输线图案布置的导电短截线图案。

公开(公告)号：US20180247897A1

公开(公告)日：2018-08-30

申请号：US15856695

申请日：2017-12-28

Applicant: SK hynix Inc.

Inventor： Won Duck JUNG ,  Sang Joon LIM ,  Sung Mook LIM

IPC: H01L23/552 ,  H01L23/482 ,  H01L23/00

CPC classification number: H01L23/552 ,  H01L23/4824 ,  H01L24/02 ,  H01L24/10 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: Disclosed is a semiconductor package. The semiconductor package may include a substrate a semiconductor chip mounted over a surface of the substrate such that an active surface of the semiconductor chip faces the surface of the substrate. The semiconductor chip and substrate may be configured for shielding or scattering electromagnetic waves.

公开(公告)号：US20190333865A1

公开(公告)日：2019-10-31

申请号：US16183538

申请日：2018-11-07

Applicant: SK hynix Inc.

Inventor： Bok Kyu CHOI ,  Juil EOM ,  Sang Joon LIM

IPC: H01L23/552 ,  H01L23/498

Abstract: A semiconductor package may include a chip disposed on a substrate, a conductive structure disposed on the substrate to include a conductive structure frame including a side surface facing at least one side surface of the chip and to include conductive structure fingers extending from the conductive structure frame toward an edge of the substrate, and an electromagnetic interference (EMI) shielding layer covering the chip and the conductive structure and contacting a side surface of an end of one or more of the conductive structure fingers.

公开(公告)号：US20190081009A1

公开(公告)日：2019-03-14

申请号：US16186305

申请日：2018-11-09

Applicant: SK hynix Inc.

Inventor： Won Duck JUNG ,  Sang Joon LIM ,  Sung Mook LIM

IPC: H01L23/552 ,  H01L23/482 ,  H01L23/00

Abstract: Disclosed is a semiconductor package. The semiconductor package may include a substrate a semiconductor chip mounted over a surface of the substrate such that an active surface of the semiconductor chip faces the surface of the substrate. The semiconductor chip and substrate may be configured for shielding or scattering electromagnetic waves.

公开(公告)号：US20140175680A1

公开(公告)日：2014-06-26

申请号：US14014652

申请日：2013-08-30

Applicant: SK hynix Inc.

Inventor： Eul Chul JANG ,  Qwan Ho CHUNG ,  Sang Joon LIM ,  Sung Woo HAN

IPC: H05K1/02 ,  H01L23/528

CPC classification number: H05K1/0224 ,  H01L23/49838 ,  H01L23/552 ,  H01L2924/0002 ,  H05K1/0219 ,  H05K1/0253 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09345 ,  H05K2201/09681 ,  H05K2201/097 ,  H05K2201/09727 ,  H01L2924/00

Abstract: Package substrates are provided. The package substrate may include a power line and a ground line on a first surface of a substrate body; a plurality of signal lines on the first surface between the power line and the ground line; and a lower ground pattern and a lower power pattern positioned on a second surface of the substrate body opposite to the first surface. The lower ground pattern may be disposed to be opposite to the power line and the lower power pattern may be disposed to be opposite to the ground line. Related semiconductor packages are also provided.

Abstract translation: 提供封装衬底。 封装基板可以包括在基板主体的第一表面上的电源线和接地线; 电源线和接地线之间的第一表面上的多条信号线; 以及位于基板主体的与第一表面相对的第二表面上的较低接地图案和较低功率图案。 下接地图案可以被布置成与电力线相对，并且下功率图案可以被设置为与接地线相对。 还提供了相关的半导体封装。

公开(公告)号：US20130078807A1

公开(公告)日：2013-03-28

申请号：US13680668

申请日：2012-11-19

Applicant: SK HYNIX INC.

Inventor： Chang Jun PARK ,  Kwon Whan HAN ,  Seong Cheol KIM ,  Sung Min KIM ,  Hyeong Seok CHOI ,  Ha Na LEE ,  Tac Keun OH ,  Sang Joon LIM

IPC: H01L21/48

CPC classification number: H01L21/486 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/367 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/94 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/3025 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00

Abstract: A wafer level chip scale package having an enhanced heat exchange efficiency with an EMF shield is presented. The wafer level chip scale package includes a semiconductor chip, an insulation layer, and a metal plate. The semiconductor chip has a plurality of bonding pads on an upper face thereof. The insulation layer is disposed over the upper face of the semiconductor chip and has openings that expose some portions of the bonding pads. The metal plate covers an upper face of the insulation layer and side faces of the semiconductor chip in which the metal plate is electrically insulated from the bonding pads.