公开(公告)号：US20190027434A1

公开(公告)日：2019-01-24

申请号：US15923737

申请日：2018-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-jin JUNG ,  Joon-hee LEE

IPC: H01L23/528 ,  H01L27/11556 ,  H01L27/11582

Abstract: Provided is an integrated circuit device including a plurality of word lines overlapping each other, in a vertical direction, on a substrate, a plurality of channel structures extending in the vertical direction through the plurality of word lines on an area of the substrate, a plurality of bit line contact pads on the plurality of channel structures, and a plurality or bit lines, wherein the plurality of bit lines include a plurality of first bit lines extending parallel to each other at a first pitch in a center region of the area, and a plurality of second bit lines extending at a second pitch in an edge region of the area, the second pitch being different from the first pitch.

公开(公告)号：US20150102506A1

公开(公告)日：2015-04-16

申请号：US14511149

申请日：2014-10-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： In-sang SONG ,  In-Ku KANG ,  Joon-hee LEE ,  Kyung-man KIM

IPC: H01L25/10

CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/60 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0235 ,  H01L2224/02379 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05008 ,  H01L2224/05012 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/05564 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/06135 ,  H01L2224/29034 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45169 ,  H01L2224/454 ,  H01L2224/45565 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48148 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/4866 ,  H01L2224/48666 ,  H01L2224/48681 ,  H01L2224/48684 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/4876 ,  H01L2224/48766 ,  H01L2224/48781 ,  H01L2224/48784 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/4886 ,  H01L2224/48866 ,  H01L2224/48881 ,  H01L2224/48884 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83365 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2224/8546 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/10333 ,  H01L2924/10335 ,  H01L2924/13091 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/14511 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The semiconductor package includes: a package substrate comprising a bonding pad; a plurality of semiconductor chips stacked on the package substrate; and a bonding wire configured to electrically connect the semiconductor chips and the bonding pad. For at least one of the plurality of semiconductor chips: the semiconductor chip comprises: a semiconductor device; a first pad electrically connected to the semiconductor device; a conductive pattern; and a second pad electrically connected to the first pad, spaced apart from the conductive pattern, and extending over the conductive pattern; and the bonding wire is connected to the second pad.

Abstract translation: 半导体封装包括：封装衬底，其包括焊盘; 堆叠在所述封装基板上的多个半导体芯片; 以及被配置为电连接半导体芯片和接合焊盘的接合线。 对于所述多个半导体芯片中的至少一个半导体芯片，所述半导体芯片包括：半导体器件; 电连接到所述半导体器件的第一焊盘; 导电图案; 以及第二焊盘，其电连接到所述第一焊盘，与所述导电图案间隔开并且延伸穿过所述导电图案; 并且接合线连接到第二焊盘。

公开(公告)号：US20190267321A1

公开(公告)日：2019-08-29

申请号：US16410266

申请日：2019-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-jin Jung ,  Joon-hee LEE

IPC: H01L23/528 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11556

Abstract: Provided is an integrated circuit device including a plurality of word lines overlapping each other, in a vertical direction, on a substrate, a plurality of channel structures extending in the vertical direction through the plurality of word lines on an area of the substrate, a plurality of bit line contact pads on the plurality of channel structures, and a plurality of bit lines, wherein the plurality of bit lines include a plurality of first bit lines extending parallel to each other at a first pitch in a center region of the area, and a plurality of second bit lines extending at a second pitch in an edge region of the area, the second pitch being different from the first pitch.