公开(公告)号：US20240072060A1

公开(公告)日：2024-02-29

申请号：US18499258

申请日：2023-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： BYOUNGHAK HONG ,  SEUNGHYUN SONG ,  KI-IL KIM ,  GUNHO JO ,  KANG-ILL SEO

IPC: H01L27/12 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/088

CPC classification number: H01L27/1203 ,  H01L21/8221 ,  H01L21/823412 ,  H01L21/823456 ,  H01L21/84 ,  H01L27/088

Abstract: Nanosheet transistor devices are provided. A nanosheet transistor device includes a transistor stack that includes a lower nanosheet transistor having a first nanosheet width and a lower gate width. The transistor stack also includes an upper nanosheet transistor that is on the lower nanosheet transistor and that has a second nanosheet width and an upper gate width that are different from the first nanosheet width and the lower gate width, respectively. Related methods of forming a nanosheet transistor device are also provided.

公开(公告)号：US20220336456A1

公开(公告)日：2022-10-20

申请号：US17361381

申请日：2021-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： BYOUNGHAK HONG ,  Seunghyun Song

IPC: H01L27/092 ,  H01L25/07 ,  H01L27/06 ,  H01L29/06

Abstract: Integrated circuit devices may include a lower transistor and an upper transistor stacked on a substrate, and the upper transistor may overlap the lower transistor. The upper transistor may include an upper gate structure, and the lower transistor may include a lower gate structure, and the upper gate structure and the lower gate structure may have different widths in a horizontal direction.

公开(公告)号：US20230275021A1

公开(公告)日：2023-08-31

申请号：US17738393

申请日：2022-05-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： BYOUNGHAK HONG ,  Jeonghyuk Yim ,  Inchan Hwang ,  Gilhwan Son ,  Seungyoung Lee ,  Saehan Park ,  Janggeun Lee ,  Myunghoon Jung ,  Seungchan Yun ,  Buhyun Ham ,  Kang-ILL Seo

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/302 ,  H01L21/8234

CPC classification number: H01L23/5286 ,  H01L23/5283 ,  H01L23/5226 ,  H01L21/302 ,  H01L21/823475

Abstract: Integrated circuit devices may include a transistor, a passive device, a substrate extending between the transistor and the passive device and a power rail. The passive device may be spaced apart from the substrate. Each of the passive device and the power rail may have a first surface facing the substrate, and the first surface of the passive device is closer than the first surface of the power rail to the substrate.

公开(公告)号：US20220367521A1

公开(公告)日：2022-11-17

申请号：US17382149

申请日：2021-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： BYOUNGHAK HONG ,  SEUNGHYUN SONG ,  MYUNGGIL KANG ,  KANG-ILL SEO

IPC: H01L27/12 ,  H01L23/535 ,  G01R27/02

Abstract: Resistance measuring structures for a stacked integrated circuit device are provided. The resistance measuring structures may include a first Complementary Field Effect Transistor (CFET) stack, a second CFET stack, and a conductive connection. The first CFET may include a first upper transistor that includes a first upper drain region and a first lower transistor that is between the substrate and the first upper transistor and includes a first lower drain region. The second CFET may include a second upper transistor that includes a second upper drain region and a second lower transistor that is between the substrate and the second upper transistor and includes a second lower drain region. The conductive connection may electrically connect the first upper drain region and the second upper drain region.

公开(公告)号：US20240145479A1

公开(公告)日：2024-05-02

申请号：US18406345

申请日：2024-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： BYOUNGHAK HONG ,  SEUNGHYUN SONG ,  MYUNGGIL KANG ,  KANG-ILL SEO

IPC: H01L27/12 ,  G01R27/02 ,  H01L23/535

CPC classification number: H01L27/1203 ,  G01R27/02 ,  H01L23/535 ,  H01L27/1211

Abstract: Resistance measuring structures for a stacked integrated circuit device are provided. The resistance measuring structures may include a first Complementary Field Effect Transistor (CFET) stack, a second CFET stack, and a conductive connection. The first CFET may include a first upper transistor that includes a first upper drain region and a first lower transistor that is between the substrate and the first upper transistor and includes a first lower drain region. The second CFET may include a second upper transistor that includes a second upper drain region and a second lower transistor that is between the substrate and the second upper transistor and includes a second lower drain region. The conductive connection may electrically connect the first upper drain region and the second upper drain region.

公开(公告)号：US20230326813A1

公开(公告)日：2023-10-12

申请号：US17837453

申请日：2022-06-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： BYOUNGHAK HONG ,  Wookhyun Kwon ,  Hyoeun Park ,  Kangill Seo

IPC: H01L21/66

CPC classification number: H01L22/34

Abstract: Integrated circuit devices may include a cell transistor and a parameter measuring structure (e.g., a resistance measuring structure). The cell transistor may be on a first surface of a substrate structure, which is opposite a second surface thereof. The parameter measuring structure may include first and second contact structures that extend through the substrate structure. The second surface of the substrate structure may expose respective portions of the first and second contact structures.

公开(公告)号：US20220344481A1

公开(公告)日：2022-10-27

申请号：US17366534

申请日：2021-07-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： BYOUNGHAK HONG ,  Seunghyun Song ,  Inchan Hwang

IPC: H01L29/417 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/423 ,  H01L29/40

Abstract: Integrated circuit devices may include a lower transistor and an upper transistor stacked on a substrate and may include a conductive contact. The upper transistor may include an upper source/drain region that overlaps a lower source/drain region of the lower transistor. The conductive contact may contact a side surface of the upper source/drain region and may overlap a center portion of the lower source/drain region. The side surface of the upper source/drain region may include a protrusion and a recess.

公开(公告)号：US20240355824A1

公开(公告)日：2024-10-24

申请号：US18757829

申请日：2024-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： BYOUNGHAK HONG ,  SEUNGHYUN SONG

IPC: H01L27/092 ,  H01L21/8238 ,  H01L25/07 ,  H01L27/06 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L27/0922 ,  H01L21/82385 ,  H01L25/074 ,  H01L27/0688 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/42392

Abstract: Integrated circuit devices may include a lower transistor and an upper transistor stacked on a substrate, and the upper transistor may overlap the lower transistor. The upper transistor may include an upper gate structure, and the lower transistor may include a lower gate structure, and the upper gate structure and the lower gate structure may have different widths in a horizontal direction.

公开(公告)号：US20230361112A1

公开(公告)日：2023-11-09

申请号：US17936127

申请日：2022-09-28

Applicant: Samsung Electronics Co.; Ltd.

Inventor： BYOUNGHAK HONG ,  Gunho Jo ,  Sooyoung Park ,  Hyoeun Park ,  WookHyun Kwon ,  Jaehong Lee ,  Kang-Ill Seo

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/735 ,  H01L29/861

CPC classification number: H01L27/067 ,  H01L29/0673 ,  H01L29/735 ,  H01L29/8613

Abstract: Integrated circuit devices including a bipolar junction transistor (BJT) and/or a P-N junction diode are provided. The integrated circuit devices may include a first stack including first and second semiconductor regions that are spaced apart from each other in a horizontal direction and have a first conductivity type and a plurality of nano-semiconductor layers that are stacked in a vertical direction and are between the first and second semiconductor regions. The plurality of nano-semiconductor layers each have a second conductivity type, and the first semiconductor region may include a side surface facing the plurality of nano-semiconductor layers. The integrated circuit device may also include a vertical semiconductor layer having the second conductivity type and a conductive contact that contacts the plurality of nano-semiconductor layers. The vertical semiconductor layer may contact the side surface of the first semiconductor region and the plurality of nano-semiconductor layers.

公开(公告)号：US20230163073A1

公开(公告)日：2023-05-25

申请号：US17576007

申请日：2022-01-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： GILHWAN SON ,  HOONSEOK SEO ,  SAEHAN PARK ,  BYOUNGHAK HONG ,  KANG-ILL SEO

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/535

CPC classification number: H01L23/5286 ,  H01L21/76898 ,  H01L23/535

Abstract: Methods of forming an integrated circuit devices may include forming a transistor on a first surface of a substrate. The transistor may include an active region, a source/drain region contacting the active region and a gate electrode on the active region. The methods may also include forming a conductive wire that is electrically connected to the source/drain region, forming a trench extending through the substrate by etching a second surface of the substrate, which is opposite the first surface of the substrate, and forming a power rail in the trench. The power rail is electrically connected to conductive wire.