公开(公告)号：US20230361112A1

公开(公告)日：2023-11-09

申请号：US17936127

申请日：2022-09-28

Applicant: Samsung Electronics Co.; Ltd.

Inventor： BYOUNGHAK HONG ,  Gunho Jo ,  Sooyoung Park ,  Hyoeun Park ,  WookHyun Kwon ,  Jaehong Lee ,  Kang-Ill Seo

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/735 ,  H01L29/861

CPC classification number: H01L27/067 ,  H01L29/0673 ,  H01L29/735 ,  H01L29/8613

Abstract: Integrated circuit devices including a bipolar junction transistor (BJT) and/or a P-N junction diode are provided. The integrated circuit devices may include a first stack including first and second semiconductor regions that are spaced apart from each other in a horizontal direction and have a first conductivity type and a plurality of nano-semiconductor layers that are stacked in a vertical direction and are between the first and second semiconductor regions. The plurality of nano-semiconductor layers each have a second conductivity type, and the first semiconductor region may include a side surface facing the plurality of nano-semiconductor layers. The integrated circuit device may also include a vertical semiconductor layer having the second conductivity type and a conductive contact that contacts the plurality of nano-semiconductor layers. The vertical semiconductor layer may contact the side surface of the first semiconductor region and the plurality of nano-semiconductor layers.

公开(公告)号：US11322602B2

公开(公告)日：2022-05-03

申请号：US16794358

申请日：2020-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwi Chan Jun ,  Kang-Ill Seo ,  Jeong Hyuk Yim

IPC: H01L29/66 ,  H01L29/78

Abstract: Vertical field-effect transistor (VFET) devices and methods of forming VFET devices are provided. The methods may include forming a preliminary VFET on a substrate. The preliminary VFET may include a bottom source/drain region on the substrate, a channel region on the bottom source/drain region, a top source/drain region on the channel region, a patterned sacrificial layer on a side surface of the channel region, and an insulating layer. The top source/drain region and the patterned sacrificial layer may be enclosed by the insulating layer. The methods may also include forming a contact opening extending through the insulating layer and exposing a portion of the patterned sacrificial layer, forming a cavity between the channel region and the insulating layer by removing the patterned sacrificial layer through the contact opening, and forming a gate electrode in the cavity.

公开(公告)号：US09614068B2

公开(公告)日：2017-04-04

申请号：US14843231

申请日：2015-09-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kang-Ill Seo

IPC: H01L29/06 ,  H01L29/775 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/775 ,  B82Y10/00 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/78696

Abstract: A semiconductor device includes a first active region, a field insulating layer disposed in the first active region, a first nanowire pattern disposed on the first active region and extended in a first direction, and a first gate disposed on the first active region and extended in a second direction crossing the first direction. The first gate covers the first nanowire pattern. The semiconductor device further includes a source or drain epitaxial layer disposed on at least one side of the first nanowire pattern. The first gate includes a first region disposed on the first nanowire pattern and having a first width, and a second region disposed beneath the first nanowire pattern and having a second width wider than the first width.

公开(公告)号：US09570434B2

公开(公告)日：2017-02-14

申请号：US15217531

申请日：2016-07-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Jae Kang ,  Jin-Wook Lee ,  Kang-Ill Seo ,  Yong-Min Cho

IPC: H01L27/088 ,  H01L27/02 ,  H01L23/522 ,  H01L21/768 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  G03F7/70 ,  H01L21/0274 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53271 ,  H01L27/0207

Abstract: Provided are a semiconductor device and a fabricating method thereof. The fabricating method includes forming first to fourth fins, each extending in a first direction, to be spaced apart in a second direction intersecting the first direction, forming first and second gate lines, each extending in the second direction, on the first to fourth fins to be spaced apart in the first direction, forming a first contact on the first gate line between the first and second fins, forming a second contact on the first gate line between the third and fourth fins, forming a third contact on the second gate line between the first and second fins, forming a fourth contact on the second gate line between the third and fourth fins and forming a fifth contact on the first to fourth contacts so as to overlap with the second contact and the third contact and so as not to overlap with the first contact and the fourth contact, wherein the fifth contact is arranged to diagonally traverse a quadrangle defined by the first to fourth contacts.

Abstract translation: 提供一种半导体器件及其制造方法。 制造方法包括：形成第一至第四鳍片，每个翼片沿第一方向延伸，沿与第一方向相交的第二方向间隔开，形成第一和第二栅极线，每个沿第二方向延伸，第一至第四鳍片 在第一方向上间隔开，在第一和第二鳍之间的第一栅极线上形成第一接触，在第三和第四鳍之间的第一栅极线上形成第二接触，在第二栅极线上形成第三接触 在第一和第二散热片之间，在第三和第四鳍之间的第二栅极线上形成第四触点，并在第一至第四触点上形成第五触点，以便与第二触点和第三触点重叠， 与第一触点和第四触点重叠，其中第五触点布置成对角地横过由第一至第四触点限定的四边形。

公开(公告)号：US20160380084A1

公开(公告)日：2016-12-29

申请号：US15234484

申请日：2016-08-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JONG-HYUK KIM ,  Kang-Ill Seo ,  Hyun-Jae Kang ,  Deok-Han Bae

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/308

CPC classification number: H01L29/66795 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139

Abstract: A method of fabricating a semiconductor device is provided. A plurality of target patterns is formed on a substrate. The plurality of target patterns is extended in parallel to each other along a first direction. A first mask pattern extending in the first direction and including a plurality of first openings is formed. A second mask pattern extending in a second direction crossing the first direction and including a plurality of second openings is formed. Each second opening overlaps each first opening to form an overlapped opening region. A region of the plurality of target patterns is etched through the overlapped opening region using the first mask pattern and the second mask pattern as a etch mask. The region of the plurality of target patterns is overlapped with the overlapped opening region.

公开(公告)号：US12230571B2

公开(公告)日：2025-02-18

申请号：US17576007

申请日：2022-01-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gilhwan Son ,  Hoonseok Seo ,  Saehan Park ,  Byounghak Hong ,  Kang-Ill Seo

IPC: H01L23/528 ,  H01L21/74 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/485 ,  H01L23/535 ,  H01L27/088

Abstract: Methods of forming an integrated circuit devices may include forming a transistor on a first surface of a substrate. The transistor may include an active region, a source/drain region contacting the active region and a gate electrode on the active region. The methods may also include forming a conductive wire that is electrically connected to the source/drain region, forming a trench extending through the substrate by etching a second surface of the substrate, which is opposite the first surface of the substrate, and forming a power rail in the trench. The power rail is electrically connected to conductive wire.

公开(公告)号：US20240355878A1

公开(公告)日：2024-10-24

申请号：US18456571

申请日：2023-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEUNG MIN SONG ,  Panjae Park ,  Kang-Ill Seo

IPC: H01L29/06 ,  H01L21/8234 ,  H01L25/07 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/823412 ,  H01L25/074 ,  H01L27/088 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: Integrated circuit devices may include an upper transistor structure on a substrate, the upper transistor structure comprising an upper channel region and an upper gate electrode on the upper channel region; a lower transistor structure between the substrate and the upper transistor structure, the lower transistor structure comprising a lower channel region and a lower gate electrode on the lower channel region; and an intergate contact between the lower gate electrode and the upper gate electrode. The lower gate electrode may be electrically connected to the upper gate electrode through the intergate contact, and a portion of a lower surface of the intergate contact may protrude beyond a side surface of the lower gate electrode.

公开(公告)号：US20240332131A1

公开(公告)日：2024-10-03

申请号：US18448482

申请日：2023-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： JINTAE KIM ,  Keumseok Park ,  Kang-Ill Seo

IPC: H01L23/48 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/0688 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: Integrated circuit devices may include a power switch cell including an upper transistor on a substrate and a lower transistor between the substrate and the upper transistor. The upper transistor may include an upper channel region, first and second upper source/drain regions, and an upper gate electrode on the upper channel region. The lower transistor may include a lower channel region, first and second lower source/drain regions, and a lower gate electrode on the lower channel region. The first and second upper source/drain regions and the first and second lower source/drain regions may have the same conductivity type, the first upper source/drain region and the first lower source/drain region may be electrically connected to each other, the second upper source/drain region and the second lower source/drain region may be electrically connected to each other, and the upper and lower gate electrodes may be electrically connected to each other.

公开(公告)号：US09905559B2

公开(公告)日：2018-02-27

申请号：US15612416

申请日：2017-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Il Bae ,  Kang-Ill Seo

IPC: H01L27/088 ,  H01L21/31 ,  H01L29/06 ,  H01L29/78 ,  H01L29/161 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/3105 ,  H01L29/786 ,  H01L29/775 ,  H01L29/08 ,  H01L29/423

CPC classification number: H01L27/0886 ,  H01L21/31053 ,  H01L21/823431 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/78696

Abstract: A semiconductor device includes a first fin structure disposed on a substrate. The first fin structure extends in a first direction. A first sacrificial layer pattern is disposed on the first fin structure. The first sacrificial layer pattern includes a left portion and a right portion arranged in the first direction. A dielectric layer pattern is disposed on the first fin structure and interposed between the left and right portions of the first sacrificial layer pattern. A first active layer pattern extending in the first direction is disposed on the first sacrificial layer pattern and the dielectric layer pattern. A first gate electrode structure is disposed on a portion of the first active layer pattern. The portion of the first active layer is disposed on the dielectric layer pattern. The first gate electrode structure extends in a second direction crossing the first direction.

公开(公告)号：US20170162651A1

公开(公告)日：2017-06-08

申请号：US14961213

申请日：2015-12-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNG-DAE SUK ,  Bom-Soo Kim ,  Kang-Ill Seo

IPC: H01L29/06 ,  H01L27/12 ,  H01L29/51 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L27/1211 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/511 ,  H01L29/66439 ,  H01L29/785

Abstract: A semiconductor device includes a wire pattern spaced apart from a substrate and extended in a first direction, a gate electrode disposed around a circumference of the wire pattern and extended in a second direction that is different from the first direction, a source disposed on a first side of the gate electrode, a drain disposed on a second side of the gate electrode, the source and the drain connected to the wire pattern and a gate spacer disposed on first and second sidewalls of the gate electrode, on the source and on the drain.