公开(公告)号：US20240178274A1

公开(公告)日：2024-05-30

申请号：US18366922

申请日：2023-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gunho Jo ,  Heesub Kim ,  Seung Hyun Lim ,  Bomi Kim ,  Eunho Cho

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/0673 ,  H01L27/092 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/775

Abstract: An integrated circuit device includes a first fin-type active region and a second fin-type active region, a device isolation film adjacent to each of the first and second fin-type active regions, a first gate line on the first fin-type active region, a second gate line on the second fin-type active region, and a gate cut insulating pattern separating the first and second gate lines, wherein the device isolation film includes a first local isolation portion and a second local isolation portion, which are separating the first fin-type active region from the second fin-type active region to be apart from each other with the gate cut insulating pattern therebetween.

公开(公告)号：US20230361112A1

公开(公告)日：2023-11-09

申请号：US17936127

申请日：2022-09-28

Applicant: Samsung Electronics Co.; Ltd.

Inventor： BYOUNGHAK HONG ,  Gunho Jo ,  Sooyoung Park ,  Hyoeun Park ,  WookHyun Kwon ,  Jaehong Lee ,  Kang-Ill Seo

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/735 ,  H01L29/861

CPC classification number: H01L27/067 ,  H01L29/0673 ,  H01L29/735 ,  H01L29/8613

Abstract: Integrated circuit devices including a bipolar junction transistor (BJT) and/or a P-N junction diode are provided. The integrated circuit devices may include a first stack including first and second semiconductor regions that are spaced apart from each other in a horizontal direction and have a first conductivity type and a plurality of nano-semiconductor layers that are stacked in a vertical direction and are between the first and second semiconductor regions. The plurality of nano-semiconductor layers each have a second conductivity type, and the first semiconductor region may include a side surface facing the plurality of nano-semiconductor layers. The integrated circuit device may also include a vertical semiconductor layer having the second conductivity type and a conductive contact that contacts the plurality of nano-semiconductor layers. The vertical semiconductor layer may contact the side surface of the first semiconductor region and the plurality of nano-semiconductor layers.

公开(公告)号：US20230086084A1

公开(公告)日：2023-03-23

申请号：US17554483

申请日：2021-12-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungchan Yun ,  Inchan Hwang ,  Gunho Jo ,  Jeonghyuk Yim ,  Byounghak Hong ,  Kang-ill Seo ,  Ming He ,  JaeHyun Park ,  Mehdi Saremi ,  Rebecca Park ,  Harsono Simka ,  Daewon Ha

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L27/088 ,  H01L29/417 ,  H01L21/8234

Abstract: Transistor devices are provided. A transistor device includes a substrate. The transistor device includes a lower transistor having a lower gate and a lower channel region on the substrate. The transistor device includes an upper transistor having an upper gate and an upper channel region. The lower transistor is between the upper transistor and the substrate. The transistor device includes an isolation region that separates the lower channel region of the lower transistor from the upper channel region of the upper transistor. Moreover, the lower gate of the lower transistor contacts the upper gate of the upper transistor. Related methods of forming a transistor device are also provided.

公开(公告)号：US20240379550A1

公开(公告)日：2024-11-14

申请号：US18641698

申请日：2024-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heeseop Kim ,  Gunho Jo ,  Bomi Kim ,  Eunho Cho

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor device includes a substrate having an active region extending in a first direction, a gate structure on the active region, intersecting the active region and extending in a second direction, a source/drain region adjacent the gate structure and on the active region, a contact plug on the source/drain region and electrically connected to the source/drain regions, a first power structure on one side of the source/drain region in the second direction and electrically connected to the contact plug, and a second power structure penetrating the substrate and on a lower end of the first power structure. The first power structure and the second power structure are integrated as a unitary structure, and the first power structure has a first width at an upper thereof and a second width at the lower end thereof, the second width being equal to or greater than the first width.

公开(公告)号：US20240274677A1

公开(公告)日：2024-08-15

申请号：US18370249

申请日：2023-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gunho Jo ,  Chulsung Kim ,  Bomi Kim ,  Heesub Kim ,  Eunho Cho

IPC: H01L29/417 ,  H01L23/48 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L23/481 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: An integrated circuit device includes fin-type active regions protruding from a substrate and extending lengthwise in a first horizontal direction, source/drain regions respectively arranged on the fin-type active regions, a device isolation film covering both sidewalls of each fin-type active region, an insulating structure covering the source/drain regions and the device isolation film, source/drain contacts respectively arranged on and connected to the source/drain regions and apart from each other in a second horizontal direction perpendicular to the first horizontal direction, and a contact isolation insulating film arranged between the source/drain contacts in the second horizontal direction and having a lower surface closer to the substrate than a lower surface of each source/drain contact. At least one of the source/drain contacts includes a first portion extending in a vertical direction toward the substrate along a surface of the contact isolation insulating film.

公开(公告)号：US20240170483A1

公开(公告)日：2024-05-23

申请号：US18347919

申请日：2023-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gunho Jo ,  Heesub Kim ,  Seung Hyun Lim ,  Bomi Kim ,  Eunho Cho

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/528

CPC classification number: H01L27/088 ,  H01L21/823475 ,  H01L23/5286

Abstract: An integrated circuit device includes a fin-type active region including a first fin portion and a second fin portion apart from each other in a first lateral direction with a contact space therebetween, a first source/drain region on the fin-type active region at a position overlapping the contact space in a vertical direction, a gate line on the first fin portion, a device isolation film covering both sidewalls of each of the first and second fin portions and defining a width of the contact space, a back side source/drain contact electrically connected to the first source/drain region, filling the contact space, and having a sidewall facing each of the first and second fin portions and the device isolation film, and an etch stop layer contacting a top surface of each of the first and second fin portions between the first fin portion and the gate line.

公开(公告)号：US11843001B2

公开(公告)日：2023-12-12

申请号：US17380999

申请日：2021-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Ki-Il Kim ,  Gunho Jo ,  Kang-Ill Seo

IPC: H04L45/745 ,  H04L12/46 ,  H04L45/52 ,  H01L27/12 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/822 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/8221 ,  H01L21/823412 ,  H01L21/823456 ,  H01L21/84 ,  H01L27/088

Abstract: Nanosheet transistor devices are provided. A nanosheet transistor device includes a transistor stack that includes a lower nanosheet transistor having a first nanosheet width and a lower gate width. The transistor stack also includes an upper nanosheet transistor that is on the lower nanosheet transistor and that has a second nanosheet width and an upper gate width that are different from the first nanosheet width and the lower gate width, respectively. Related methods of forming a nanosheet transistor device are also provided.

公开(公告)号：US12255099B2

公开(公告)日：2025-03-18

申请号：US17590863

申请日：2022-02-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gunho Jo ,  Ki-il Kim ,  Byounghak Hong

IPC: H01L21/822 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: Methods of forming a plurality of transistor stacks are provided. A method of forming a plurality of transistor stacks includes etching a plurality of nanosheets, using a plurality of spacers that are on sidewalls of a plurality of semiconductor fins as an etch mask, to provide a plurality of spaced-apart nanosheet stacks that each have at least one of the semiconductor fins thereon.

公开(公告)号：US12224314B2

公开(公告)日：2025-02-11

申请号：US17402214

申请日：2021-08-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gunho Jo ,  Ki-il Kim ,  Byounghak Hong ,  Kang-ill Seo

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: A multi-stack semiconductor device includes: a substrate; and a plurality of multi-stack transistor structures arranged on the substrate in a channel width direction, wherein the multi-stack transistor structure include at least one lower transistor structure and at least one upper transistor structure stacked above the lower transistor structure, wherein the lower and upper transistor structures include at least one channel layer as a current channel, wherein the lower transistor structures of at least two multi-stack transistor structures have different channel-layer widths.

公开(公告)号：US20230343824A1

公开(公告)日：2023-10-26

申请号：US17964677

申请日：2022-10-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungchan YUN ,  Jaejik Baek ,  Gunho Jo ,  Byounghak Hong ,  Kang-ill Seo

IPC: H01L29/06 ,  H01L25/11 ,  H01L29/786 ,  H01L21/8234

CPC classification number: H01L29/0673 ,  H01L25/117 ,  H01L29/78696 ,  H01L21/823412 ,  H01L29/78672

Abstract: Provided is a multi-stack semiconductor device that includes: a substrate; a lower field-effect transistor in which a lower channel structure is surrounded by a lower gate structure including a lower work-function metal layer and a lower gate electrode; and an upper field-effect transistor in which an upper channel structure is surrounded by an upper gate structure including an upper work-function metal layer and an upper gate electrode, wherein each of the lower gate electrode and the upper gate electrode includes a metal or a metal compound, and wherein the lower gate electrode comprises polycrystalline silicon (poly-Si) or poly-Si comprising a dopant, and the upper gate electrode comprises a metal or a metal compound.