公开(公告)号：US12074572B2

公开(公告)日：2024-08-27

申请号：US17263044

申请日：2020-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunseok Choi ,  Jooseung Kim ,  Jihoon Kim ,  Hyoseok Na ,  Sanghun Sim ,  Namjun Cho

IPC: H03F1/52 ,  H02H3/087 ,  H03F3/24

CPC classification number: H03F1/52 ,  H02H3/087 ,  H03F3/245 ,  H03F2200/462

Abstract: An electronic device and method thereof of are provided to prevent burnout due to overcurrent. An electronic device includes a power amplifier configured to amplify a transmission signal; a battery configured to provide a bias voltage to the at least one power amplifier; and an overcurrent protection circuit configured to prevent overcurrent from flowing through the power amplifier. The overcurrent protection circuit includes a configurer configured to configure a reference current value, based on the power amplifier; a measurer configured to measure a bias current value due to the bias voltage; a comparator configured to compare the measured bias current value with the reference current value; and a controller configured to recognize overcurrent flowing through the power amplifier and control provision of the bias voltage, based on a result of the comparison.

公开(公告)号：US20240055372A1

公开(公告)日：2024-02-15

申请号：US18315689

申请日：2023-05-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ae-Nee Jang ,  Jihoon Kim ,  Seungduk Baek ,  Hyuekjae Lee

IPC: H01L23/00 ,  H01L25/065 ,  H10B80/00

CPC classification number: H01L23/562 ,  H01L24/08 ,  H01L24/05 ,  H01L24/06 ,  H01L25/0657 ,  H10B80/00 ,  H01L24/94 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/05647 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/05571 ,  H01L2224/05582 ,  H01L2224/05644 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2224/05013 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1443 ,  H01L2924/1438 ,  H01L2224/94 ,  H01L2224/80895

Abstract: A semiconductor device includes a substrate and a lower die on the substrate. The lower die includes a first semiconductor substrate having a first device region and a first edge region therein, a first semiconductor element on the first device region, a first pad on the first device region and on the first semiconductor element, and a first interconnection structure connecting the first semiconductor element to the first pad. The first interconnection structure includes a first signal pattern on the first device region and connected to the first semiconductor element, a second signal pattern on the first device region and directly connected to the first pad, and a first dummy pattern at the same level as the second signal pattern and disposed on the first edge region. An upper die is provided, which is bonded to the lower die such that the first pad of the lower die is in contact with a second pad of the upper die.

公开(公告)号：US20240047389A1

公开(公告)日：2024-02-08

申请号：US18141675

申请日：2023-05-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonmin Lee ,  Jihoon Kim ,  Aenee Jang

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/05 ,  H01L24/80 ,  H01L24/94 ,  H01L24/96 ,  H01L25/0657 ,  H01L24/08 ,  H01L24/06 ,  H01L2924/1431 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2224/95001 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1434 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2224/80203 ,  H01L2224/08145 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06133 ,  H01L2224/05007 ,  H01L2224/05187 ,  H01L2224/05124 ,  H01L2224/05647 ,  H01L2224/05015 ,  H01L2224/05018 ,  H01L2224/05082 ,  H01L2224/05541 ,  H01L2224/05555 ,  H01L2224/05558 ,  H01L2224/05687

Abstract: A semiconductor package includes a first semiconductor chip including a first substrate, a plurality of first pads disposed on a front surface of the first substrate, a first insulating layer surrounding the plurality of first pads, and a plurality of wiring patterns disposed between the first substrate and the plurality of first pads and electrically connected to the plurality of first pads; and a second semiconductor chip disposed below the first semiconductor chip and including a second substrate, a plurality of second pads disposed on the second substrate and contacting the plurality of first pads, a second insulating layer surrounding the plurality of second pads and contacting the first insulating layer, and a plurality of through-electrodes penetrating through the second substrate to be connected to the plurality of second pads. The plurality of wiring patterns include top wiring patterns adjacent to the plurality of first pads in a direction perpendicular to the front surface. On a plane parallel to the front surface, within a first region having a first shape and first region area from a top down view, first top wiring patterns have a first occupied area between adjacent first pads of a first group of first pads from among the plurality of first pads, and within a second region having the first shape and first region area from a top down view, second top wiring patterns have a second occupied area, larger than the first occupied area, between adjacent first pads of a second group of first pads from among the plurality of first pads. From a top down view, each pad of the first group of first pads has a first area, and each pad of the second group of first pads has a second area, wherein the first area is smaller than a second area.

公开(公告)号：US11875738B2

公开(公告)日：2024-01-16

申请号：US17691654

申请日：2022-03-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jihoon Kim ,  Yongsoo Lee ,  Kyunghoon Chung ,  Minje Hyun

IPC: G09G3/3225

CPC classification number: G09G3/3225 ,  G09G2310/0291 ,  G09G2320/0276 ,  G09G2320/0673 ,  G09G2330/021

Abstract: A display driver integrated circuit includes a gamma circuit, a control circuit, and an output buffer circuit. The gamma circuit generates a plurality of gamma voltages based on gamma control information, a first gamma power supply voltage and a second gamma power supply voltage. The control circuit calculates a gamma limit value based on panel brightness information, voltage levels of the first and second gamma power supply voltages and the number of the plurality of gamma voltages. The control circuit generates a mode determination signal. The output buffer circuit includes a plurality of buffer circuits. Each of the plurality of buffer circuits includes an input stage and the input stage includes first transistors and second transistors. In a first driving mode, each of the plurality of buffer circuits turns off the first transistors and turns on the second transistors included in the input stage.

公开(公告)号：US11829597B2

公开(公告)日：2023-11-28

申请号：US16986971

申请日：2020-08-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghyuk Lee ,  Taewon Kwak ,  Kyungmin Kim ,  Dohyeon Kim ,  Jungrim Kim ,  Jihoon Kim ,  Gibeyong Park ,  Jeongwan Park ,  Jinsu Shin ,  Konsang Lee ,  Seungcheol Lee ,  Bongje Cho ,  Munwon Choi ,  Seowon Choi ,  Eunji Choi ,  Yeunwook Lim

IPC: G06F3/04883 ,  G06F40/171 ,  G06V30/32 ,  G06V30/142

CPC classification number: G06F3/04883 ,  G06F40/171 ,  G06V30/1423 ,  G06V30/32

Abstract: Disclosed is an electronic device for processing a handwriting input and including a touch screen, a processor operatively connected with the touch screen, and a memory operatively connected with the processor, wherein the memory stores instructions, which when executed, cause the processor to control the electronic device to perform handwriting recognition for a first handwriting input of a user displayed on the touch screen, to convert the first handwriting input into a text, identify at least one of an attribute or characteristic of the first handwriting input, apply at least one of the identified attribute or characteristic to the converted text, and in response to a request for conversion of the first handwriting input, replace the first handwriting input into a text (herein after, a first rich text) to which the identified at least one of the attribute or characteristic has been applied.

公开(公告)号：US20230163088A1

公开(公告)日：2023-05-25

申请号：US18151622

申请日：2023-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuekjae Lee ,  Jongho Lee ,  Jihoon Kim ,  Taehun Kim ,  Sangcheon Park ,  Jinkyeong Seol ,  Sanghoon Lee

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L24/06 ,  H01L25/0652 ,  H01L25/18 ,  H01L24/08 ,  H01L24/32 ,  H01L24/05 ,  H01L24/13 ,  H01L25/0655 ,  H01L21/561 ,  H01L25/50 ,  H01L24/94 ,  H01L24/96 ,  H01L24/92 ,  H01L25/0657 ,  H01L2224/83099 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2224/32145 ,  H01L2224/08148 ,  H01L2224/08145 ,  H01L2224/05073 ,  H01L2224/05025 ,  H01L2224/05564 ,  H01L2224/05562 ,  H01L2224/08121 ,  H01L2224/06182 ,  H01L2224/13024 ,  H01L2224/08225 ,  H01L2224/32225 ,  H01L2224/92142 ,  H01L2224/8389 ,  H01L2224/80895

Abstract: A semiconductor package includes a first connection structure, a first semiconductor chip on an upper surface of the first connection structure, a first molding layer on the upper surface of the first connection structure and surrounding the first semiconductor chip, a first bond pad on the first semiconductor chip, a first bond insulation layer on the first semiconductor chip and the first molding layer and surrounding the first bond pad, a second bond pad directly contacting the first bond pad, a second bond insulation layer surrounding the second bond pad; and a second semiconductor chip on the second bond pad and the second bond insulation layer.

公开(公告)号：US11658148B2

公开(公告)日：2023-05-23

申请号：US16854452

申请日：2020-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuekjae Lee ,  Jihoon Kim ,  JiHwan Suh ,  So Youn Lee ,  Jihwan Hwang ,  Taehun Kim ,  Ji-Seok Hong

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L21/56

CPC classification number: H01L25/0652 ,  H01L21/565 ,  H01L24/08 ,  H01L24/80 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08146 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06524 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2225/06589

Abstract: A semiconductor package includes a substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip so that the first semiconductor chip is vertically between the second semiconductor chip and the substrate, a first molding layer adjacent to a sidewall of the first semiconductor chip on the substrate, the first molding layer formed of a first molding material, and a second molding layer adjacent to a sidewall of the second semiconductor chip on the substrate so that the first molding layer is vertically between the second molding layer and the substrate. The second molding layer is formed of a second molding material different from the first molding material. A top surface of the first semiconductor chip and a top surface of the first molding layer are flat and are coplanar with each other, and a ratio of the difference between the coefficient of thermal expansion between the second molding layer and the first molding layer to the difference between the coefficient of thermal expansion between the second molding layer and the substrate is between 5:1 and 20:1.

公开(公告)号：US11223375B2

公开(公告)日：2022-01-11

申请号：US16765813

申请日：2018-11-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungjoon Kim ,  Jiyong Kim ,  Jihoon Kim ,  Hyoseok Na

IPC: H04B1/00 ,  H01Q1/24 ,  H04B1/401

Abstract: An electronic device can comprise: a processor; a transceiver connected to the processor; a first front-end unit connected to the transceiver and performing transmission/reception at an LTE low-band frequency; a second front-end unit connected to the transceiver and performing transmission/reception at an LTE middle-band frequency and/or an LTE high-band frequency; a third front-end unit connected to the transceiver and performing transmission/reception at a 5G-band frequency; a diplexer unit connected to the first front-end unit and the second front-end unit; a filter unit connected to the third front-end unit; a first antenna connected to the diplexer unit; a second antenna connected to the filter unit; and a third antenna connected to the third front-end unit.

公开(公告)号：US11189937B2

公开(公告)日：2021-11-30

申请号：US16876716

申请日：2020-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chaejun Lee ,  Jihoon Kim ,  Jiyong Kim ,  Hyoseok Na ,  Jongin Lee

IPC: H01Q21/06 ,  H04B17/318 ,  H01Q1/24 ,  H01Q9/04 ,  H03F3/195

Abstract: An electronic device is provided The electronic device includes a patch antenna element, at least one antenna including a first feeding unit electrically connected to the patch antenna element and a second feeding unit electrically connected to the patch antenna element so as to have a designated isolation for a signal that is input to the first feeding unit, a radio frequency integrated circuit (RFIC) which includes a first communication circuit including a first transmission circuit and a first reception circuit which are electrically connected to the first feeding unit, and a second communication circuit including a second transmission circuit and a second reception circuit which are electrically connected to the second feeding unit, and a processor.

公开(公告)号：US20210358875A1

公开(公告)日：2021-11-18

申请号：US17155657

申请日：2021-01-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuekjae Lee ,  Jongho Lee ,  Jihoon Kim ,  Taehun Kim ,  Sangcheon Park ,  Jinkyeong Seol ,  Sanghoon Lee

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package includes a first connection structure, a first semiconductor chip on an upper surface of the first connection structure, a first molding layer on the upper surface of the first connection structure and surrounding the first semiconductor chip, a first bond pad on the first semiconductor chip, a first bond insulation layer on the first semiconductor chip and the first molding layer and surrounding the first bond pad, a second bond pad directly contacting the first bond pad, a second bond insulation layer surrounding the second bond pad; and a second semiconductor chip on the second bond pad and the second bond insulation layer.