公开(公告)号：US6087725A

公开(公告)日：2000-07-11

申请号：US161498

申请日：1998-09-28

申请人： Shigeo Yoshii ,  Yoichi Sasai ,  Satoshi Kamiyama ,  Tohru Saitoh ,  Takashi Nishikawa ,  Ryoko Miyanaga

发明人： Shigeo Yoshii ,  Yoichi Sasai ,  Satoshi Kamiyama ,  Tohru Saitoh ,  Takashi Nishikawa ,  Ryoko Miyanaga

IPC分类号： H01L33/28 ,  H01L33/40 ,  H01L33/00

CPC分类号： H01L33/40 ,  H01L33/28

摘要： On a substrate of n-type GaAs, an n-type cladding layer of n-type Zn.sub.0.9 Mg.sub.0.1 S.sub.0.13 Se.sub.0.87, an n-type light guiding layer of n-type ZnS.sub.0.06 Se.sub.0.94, an active layer of ZnCdSe and a p-type light guiding layer of p-type ZnS.sub.0.06 Se.sub.0.94 are successively formed. On the p-type light guiding layer, a p-type contact structure is formed. The p-type contact structure includes a first layer of p-type ZnS.sub.0.31 Se.sub.0.54 Te.sub.0.15, a second layer of ZnS.sub.0.47 Se.sub.0.28 Te.sub.0.25, a third layer of p-type ZnS.sub.0.65 Te.sub.0.35, a fourth layer of p-type ZnS.sub.0.5 Te.sub.0.5 and a fifth layer of p-type ZnTe.

摘要翻译： 在n型GaAs的衬底上，n型Zn0.9Mg0.1S0.13Se0.87的n型覆层，n型ZnS0.06Se0.94的n型导光层，n型ZnS0.06Se0.94的有源层 ZnCdSe和p型ZnS0.06Se0.94的p型导光层依次形成。 在p型导光层上形成p型接触结构。 p型接触结构包括第一层p型ZnS0.31Se0.54Te0.15，第二层ZnS0.47Se0.28Te0.25，第三层p型ZnS0.65Te0.35，第四层 的p型ZnS0.5Te0.5和第五层p型ZnTe。

公开(公告)号：US06169296A

公开(公告)日：2001-01-02

申请号：US09176906

申请日：1998-10-22

申请人： Satoshi Kamiyama ,  Shigeo Yoshii ,  Ryoko Miyanaga ,  Takashi Nishikawa ,  Tohru Saitoh ,  Yoichi Sasai

发明人： Satoshi Kamiyama ,  Shigeo Yoshii ,  Ryoko Miyanaga ,  Takashi Nishikawa ,  Tohru Saitoh ,  Yoichi Sasai

IPC分类号： H01L3300

CPC分类号： H01L33/40 ,  H01L33/145 ,  H01L33/38 ,  H01L33/42

摘要： The light-emitting diode device of the present invention includes an active layer, a p-type contact layer, a Schottky electrode and an ohmic electrode. The active layer is formed over an n-type semiconductor substrate. The contact layer is formed over the active layer. The Schottky electrode is selectively formed on the contact layer and makes Schottky contact with the contact layer. The ohmic electrode is formed to surround the Schottky electrode on the contact layer and to be electrically connected to the Schottky electrode and transmits the light emitted from the active layer.

摘要翻译： 本发明的发光二极管器件包括有源层，p型接触层，肖特基电极和欧姆电极。 有源层形成在n型半导体衬底上。 接触层形成在有源层上。 肖特基电极选择性地形成在接触层上并与接触层进行肖特基接触。 欧姆电极形成为围绕接触层上的肖特基电极并与肖特基电极电连接并透射从有源层发射的光。

公开(公告)号：US08242025B2

公开(公告)日：2012-08-14

申请号：US12159352

申请日：2007-01-12

申请人： Takahiro Kawashima ,  Tohru Saitoh ,  Tohru Nakagawa ,  Hideo Torii

发明人： Takahiro Kawashima ,  Tohru Saitoh ,  Tohru Nakagawa ,  Hideo Torii

IPC分类号： H01L21/301

CPC分类号： H01L27/1266 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/1203 ,  H01L27/1285 ,  H01L27/1292

摘要： According to a method of the present invention for manufacturing a semiconductor piece, at least two semiconductor layers (12) are first formed on a substrate (10) by stacking a sacrificial layer (11) and the semiconductor layer (12) on the substrate (10) in this order and repeating this stacking. Next, the semiconductor layers (12) are divided into pieces by etching part of the sacrificial layers (11) and part of the semiconductor layers (12). Then, the pieces are separated from the substrate by removing the sacrificial layers (11).

摘要翻译： 根据本发明的用于制造半导体片的方法，首先通过在衬底（10）上层叠牺牲层（11）和半导体层（12）来形成至少两个半导体层（12） 10），并重复该堆叠。 接下来，通过蚀刻部分牺牲层（11）和部分半导体层（12）将半导体层（12）分割成多个。 然后，通过去除牺牲层（11）将片与衬底分离。

公开(公告)号：US20100133509A1

公开(公告)日：2010-06-03

申请号：US12451898

申请日：2008-06-04

申请人： Takahiro Kawashima ,  Tohru Saitoh

发明人： Takahiro Kawashima ,  Tohru Saitoh

IPC分类号： H01L29/775 ,  H01L21/04

CPC分类号： H01L21/02653 ,  B82Y10/00 ,  B82Y30/00 ,  C30B11/12 ,  C30B25/00 ,  C30B29/06 ,  C30B29/40 ,  C30B29/60 ,  H01L21/02521 ,  H01L21/02573 ,  H01L21/02603 ,  H01L21/02656 ,  H01L27/3262 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/775 ,  H01L33/18 ,  Y10S438/962

摘要： A method for fabricating a semiconductor nanowire that has first and second regions is provided. A catalyst particle is put on a substrate. A first source gas is introduced, thereby growing the first region from the catalyst particle via a vapor-liquid-solid phase growth. A protective coating is formed on a sidewall of the first region, and a second source gas is introduced to grow the second region extending from the first region via the liquid-solid-phase growth.

摘要翻译： 提供一种制造具有第一和第二区域的半导体纳米线的方法。 将催化剂颗粒放在基材上。 引入第一源气体，从而通过气 - 液 - 固相生长从催化剂颗粒生长第一区域。 在第一区域的侧壁上形成保护涂层，并且引入第二源气体以通过液相 - 固相生长从第一区域延伸出第二区域。

公开(公告)号：US20100012921A1

公开(公告)日：2010-01-21

申请号：US12518821

申请日：2007-11-29

申请人： Takahiro Kawashima ,  Tohru Saitoh

发明人： Takahiro Kawashima ,  Tohru Saitoh

IPC分类号： H01L29/66 ,  H01L33/00 ,  H01L31/0352 ,  H01L21/20

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/15 ,  C30B11/12 ,  C30B29/605 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/125 ,  H01L31/028 ,  H01L31/0352 ,  H01L33/18 ,  H01L43/08 ,  Y02E10/547 ,  Y10S977/762

摘要： A nanowire according to the present invention includes: a nanowire body made of a first material; and a plurality of semiconductor particle made of a second material and being contained in at least a portion of the interior of the nanowire body.

摘要翻译： 根据本发明的纳米线包括：由第一材料制成的纳米线体; 以及由第二材料制成并被包含在纳米线体的内部的至少一部分中的多个半导体颗粒。

公开(公告)号：US07586130B2

公开(公告)日：2009-09-08

申请号：US11344574

申请日：2006-02-01

申请人： Takahiro Kawashima ,  Tohru Saitoh ,  Takeshi Takagi

发明人： Takahiro Kawashima ,  Tohru Saitoh ,  Takeshi Takagi

IPC分类号： H01L29/732

CPC分类号： H01L29/78696 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/1606 ,  H01L29/42384 ,  H01L29/7781 ,  H01L29/78642 ,  Y10S977/938

摘要： A vertical field effect transistor includes: an active region with a bundle of linear structures functioning as a channel region; a lower electrode, functioning as one of source and drain regions; an upper electrode, functioning as the other of the source and drain regions; a gate electrode for controlling the electric conductivity of at least a portion of the bundle of linear structures included in the active region; and a gate insulating film arranged between the active region and the gate electrode to electrically isolate the gate electrode from the bundle of linear structures. The transistor further includes a dielectric portion between the upper and lower electrodes. The upper electrode is located over the lower electrode with the dielectric portion interposed and includes an overhanging portion sticking out laterally from over the dielectric portion. The active region is located right under the overhanging portion of the upper electrode.

摘要翻译： 垂直场效应晶体管包括：具有用作沟道区的线性结构束的有源区; 用作源极和漏极区之一的下电极; 上电极，用作源极和漏极区域中的另一个; 用于控制所述有源区域中包括的所述线性结构束的至少一部分的电导率的栅电极; 以及栅极绝缘膜，其布置在所述有源区和所述栅电极之间，以将所述栅电极与所述线结构的束电隔离。 晶体管还包括在上电极和下电极之间的电介质部分。 上电极位于下电极的上方，电介质部分插入，并且包括从电介质部分的上方横向突出的突出部分。 有源区域位于上电极的伸出部分正下方。

公开(公告)号：US07091099B2

公开(公告)日：2006-08-15

申请号：US10807307

申请日：2004-03-24

申请人： Teruhito Ohnishi ,  Koichiro Yuki ,  Tsuneichiro Sano ,  Tohru Saitoh ,  Ken Idota ,  Takahiro Kawashima ,  Shigeki Sawada

发明人： Teruhito Ohnishi ,  Koichiro Yuki ,  Tsuneichiro Sano ,  Tohru Saitoh ,  Ken Idota ,  Takahiro Kawashima ,  Shigeki Sawada

IPC分类号： H01L21/331

CPC分类号： H01L29/66242 ,  H01L29/7378

摘要： A bipolar transistor includes a Si single crystalline layer serving as a collector, a single crystalline Si/SiGeC layer and a polycrystalline Si/SiGeC layer which are formed on the Si single crystalline layer, an oxide film having an emitter opening portion, an emitter electrode, and an emitter layer. An intrinsic base layer is formed on the single crystalline Si/SiGeC layer, part of the single crystalline Si/SiGeC layer, the polycrystalline Si/SiGeC layer and the Co silicide layer together form an external base layer. The thickness of the emitter electrode is set so that boron ions implanted into the emitter electrode and diffused therein do not reach an emitter-base junction portion.

摘要翻译： 双极晶体管包括形成在Si单晶层上的Si单结晶层，单晶Si / SiGeC层和多晶Si / SiGeC层，具有发射极开口部分的氧化膜，发射极 ，和发射极层。 在单晶Si / SiGeC层上形成本征基层，单晶Si / SiGeC层的一部分，多晶Si / SiGeC层和Co硅化物层一起形成外部基极层。 发射电极的厚度被设定为使得注入发射电极并在其中扩散的硼离子不会到达发射极 - 基极接合部分。

公开(公告)号：US06930026B2

公开(公告)日：2005-08-16

申请号：US10414106

申请日：2003-04-16

申请人： Yoshihiko Kanzawa ,  Katsuya Nozawa ,  Tohru Saitoh ,  Minoru Kubo

发明人： Yoshihiko Kanzawa ,  Katsuya Nozawa ,  Tohru Saitoh ,  Minoru Kubo

IPC分类号： H01L21/205 ,  C30B33/00 ,  H01L21/20 ,  H01L29/10 ,  H01L29/165 ,  H01L29/24 ,  H01L20/30 ,  H01L21/36 ,  H01L29/06 ,  H01L29/12

CPC分类号： H01L29/1608 ,  C30B29/06 ,  C30B29/52 ,  C30B33/00 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02667 ,  H01L29/1054 ,  H01L29/165

摘要： A Si substrate 1 with a SiGeC crystal layer 8 deposited thereon is annealed to form an annealed SiGeC crystal layer 10 on the Si substrate 1. The annealed SiGeC crystal layer includes a matrix SiGeC crystal layer 7, which is lattice-relieved and hardly has dislocations, and SiC microcrystals 6 dispersed in the matrix SiGeC crystal layer 7. A Si crystal layer is then deposited on the annealed SiGeC crystal layer 10, to form a strained Si crystal layer 4 hardly having dislocations.

摘要翻译： 对其上沉积有SiGeC晶体层8的Si衬底1进行退火，以在Si衬底1上形成退火的SiGeC晶体层10。 退火的SiGeC晶体层包括晶格释放并且几乎不具有位错的矩阵SiGeC晶体层7和分散在基体SiGeC晶体层7中的SiC微晶6。 然后在退火的SiGeC晶体层10上沉积Si晶体层，以形成几乎不具有位错的应变Si晶体层4。

公开(公告)号：US20050092230A1

公开(公告)日：2005-05-05

申请号：US11009020

申请日：2004-12-13

申请人： Yoshihiko Kanzawa ,  Teruhito Ohnishi ,  Ken Idota ,  Tohru Saitoh ,  Akira Asai

发明人： Yoshihiko Kanzawa ,  Teruhito Ohnishi ,  Ken Idota ,  Tohru Saitoh ,  Akira Asai

IPC分类号： C30B1/00 ,  C30B23/02 ,  C30B25/02 ,  C30B29/52 ,  H01L21/205 ,  H01L21/31 ,  H01L21/322 ,  H01L21/324

CPC分类号： H01L21/324 ,  C30B23/02 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02661 ,  H01L21/02664 ,  H01L21/322 ,  Y10S438/933

摘要： A method for fabricating a semiconductor crystal that has a first step for forming a semiconductor crystal layer (202) that contains carbon atoms and at least one kind of Group IV element other than carbon on a substrate (201), a second step for adding an impurity that is capable of reacting with oxygen to the semiconductor crystal layer (202), and a third step for removing the carbon atoms contained in the semiconductor crystal layer (202) by reacting the carbon with the impurity. This method makes it possible to fabricate a semiconductor crystal substrate in which the concentration of interstitial carbon atoms is satisfactorily reduced, thus resulting in excellent electrical properties when the substrate is applied to a semiconductor device.

摘要翻译： 一种制造半导体晶体的方法，其具有在基板（201）上形成含有碳原子的半导体晶体层（202）和除了碳以外的至少一种第IV族元素的第一工序，第二工序用于添加 能够与氧反应的半导体晶体层（202）的杂质，以及通过使碳与杂质反应来除去半导体结晶层（202）中所含的碳原子的第三工序。 该方法可以制造其中间隙碳原子的浓度令人满意地降低的半导体晶体衬底，从而当将衬底应用于半导体器件时获得优异的电性能。

公开(公告)号：US06858454B1

公开(公告)日：2005-02-22

申请号：US10674523

申请日：2003-10-01

申请人： Yoshihiko Kanzawa ,  Tohru Saitoh ,  Takeshi Takagi ,  Katsuya Nozawa

发明人： Yoshihiko Kanzawa ,  Tohru Saitoh ,  Takeshi Takagi ,  Katsuya Nozawa

IPC分类号： G01N21/21 ,  G01N21/35 ,  H01L21/66

CPC分类号： G01N21/3563 ,  G01N21/211

摘要： A method for measuring semiconductor constituent element content utilizes the steps of: obtaining a film thickness of an SiGeC layer formed on a semiconductor substrate by evaluation using spectroscopic ellipsometry; measuring infrared absorption spectrum of the SiGeC layer; and obtaining a C content of the SiGeC layer based on the film thickness and the infrared absorption spectrum of the SiGeC layer. The method: obtaining an apparent Ge content of the SiGeC layer by evaluation using spectroscopic ellipsometry; and obtaining an actual Ge content of the SiGeC layer based on the apparent Ge content and the C content. The constituent element content of the SiGeC layer can be easily and accurately measured according to the above-mentioned method.

摘要翻译： 一种测量半导体构成元件含量的方法采用以下步骤：通过使用分光椭圆偏光度法评估在半导体衬底上形成的SiGeC层的膜厚度; 测量SiGeC层的红外吸收光谱; 并根据SiGeC层的膜厚和红外吸收光谱获得SiGeC层的C含量。 该方法：通过使用分光椭偏仪评估获得SiGeC层的表观Ge含量; 并且基于表观Ge含量和C含量获得SiGeC层的实际Ge含量。 根据上述方法可以容易且精确地测量SiGeC层的构成元素含量。