公开(公告)号：US20050161710A1

公开(公告)日：2005-07-28

申请号：US11073800

申请日：2005-03-07

申请人： Scott DeBoer ,  Husam Al-Shareef ,  Randhir Thakur ,  Dan Gealy

发明人： Scott DeBoer ,  Husam Al-Shareef ,  Randhir Thakur ,  Dan Gealy

IPC分类号： H01L21/02 ,  H01L21/316 ,  H01L21/8242 ,  H01L31/119

CPC分类号： H01L21/02326 ,  G11C17/16 ,  H01L21/02183 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/31604 ,  H01L21/31637 ,  H01L23/5252 ,  H01L27/10852 ,  H01L27/10861 ,  H01L27/112 ,  H01L27/11206 ,  H01L28/40 ,  H01L28/65 ,  H01L28/84 ,  H01L2924/0002 ,  H01L2924/00

摘要： A capacitor has a tantalum oxynitride film. One method for making the film comprises forming a bottom plate electrode and then forming a tantalum oxide film on the bottom plate electrode. Nitrogen is introduced to form a tantalum oxynitride film. A top plate electrode is formed on the tantalum oxynitride film.

公开(公告)号：US20060199311A1

公开(公告)日：2006-09-07

申请号：US11419942

申请日：2006-05-23

申请人： Scott DeBoer ,  Husam Al-Shareef ,  Randhir Thakur ,  Dan Gealy

发明人： Scott DeBoer ,  Husam Al-Shareef ,  Randhir Thakur ,  Dan Gealy

IPC分类号： H01L21/82

CPC分类号： H01L21/02326 ,  G11C17/16 ,  H01L21/02183 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/31604 ,  H01L21/31637 ,  H01L23/5252 ,  H01L27/10852 ,  H01L27/10861 ,  H01L27/112 ,  H01L27/11206 ,  H01L28/40 ,  H01L28/65 ,  H01L28/84 ,  H01L2924/0002 ,  H01L2924/00

摘要： A capacitor has a tantalum oxynitride film. One method for making the film comprises forming a bottom plate electrode and then forming a tantalum oxide film on the bottom plate electrode. Nitrogen is introduced to form a tantalum oxynitride film. A top plate electrode is formed on the tantalum oxynitride film. Embodiments include a method of operating an antifuse, comprising applying a voltage across electrodes of a capacitor having a tantalum oxynitride film and forming a hole in the tantalum oxynitride film.

摘要翻译： 电容器具有氮氧化钽膜。 制造薄膜的一种方法包括形成底板电极，然后在底板电极上形成氧化钽膜。 引入氮气以形成氮氧化钽膜。 在氮氧化钽膜上形成顶板电极。 实施例包括操作反熔丝的方法，包括在具有氮氧化钽膜的电容器的电极上施加电压并在氮氧化钽膜中形成孔。

公开(公告)号：US20050048793A1

公开(公告)日：2005-03-03

申请号：US10640309

申请日：2003-08-14

申请人： Ronald Weimer ,  Scott DeBoer ,  Dan Gealy ,  Husam Al-Shareef

发明人： Ronald Weimer ,  Scott DeBoer ,  Dan Gealy ,  Husam Al-Shareef

IPC分类号： H01L21/28 ,  H01L21/3105 ,  H01L21/314 ,  H01L21/316 ,  H01L29/51 ,  H01L21/469

CPC分类号： H01L21/3105 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/3144 ,  H01L21/31604 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  Y10S438/901

摘要： A method of fabricating a semiconductor device includes depositing a dielectric film and subjecting the dielectric film to a wet oxidation in a rapid thermal process chamber. The technique can be used, for example, in the formation of various elements in an integrated circuit, including gate dielectric films as well as capacitive elements. The tight temperature control provided by the RTP process allows the wet oxidation to be performed quickly so that the oxidizing species does not diffuse significantly through the dielectric film and diffuse into an underlying layer. In the case of capacitive elements, the technique also can help reduce the leakage current of the dielectric film without significantly reducing its capacitance.

摘要翻译： 制造半导体器件的方法包括沉积电介质膜并使电介质膜在快速热处理室中进行湿氧化。 该技术可以用于例如在集成电路中形成各种元件，包括栅介质膜以及电容元件。 通过RTP工艺提供的紧密温度控制允许快速进行湿氧化，使得氧化物质不会通过电介质膜显着扩散并扩散到下层。 在电容元件的情况下，该技术还可以有助于降低电介质膜的漏电流，而不会显着降低其电容。

公开(公告)号：US08378430B2

公开(公告)日：2013-02-19

申请号：US12705111

申请日：2010-02-12

申请人： Cancheepuram V. Srividya ,  Suraj Mathew ,  Dan Gealy

发明人： Cancheepuram V. Srividya ,  Suraj Mathew ,  Dan Gealy

IPC分类号： H01L27/11 ,  H01L21/8244

CPC分类号： H01L21/28079 ,  H01L21/265 ,  H01L21/28088 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： Transistors are provided including first and second source/drain regions, a channel region and a gate stack having a first gate dielectric over a substrate, the first gate dielectric having a dielectric constant higher than a dielectric constant of silicon dioxide, and a metal material in contact with the first gate dielectric, the metal material being doped with an inert element. Integrated circuits including the transistors and methods of forming the transistors are also provided.

摘要翻译： 提供了包括第一和第二源极/漏极区域的晶体管，沟道区域和栅极堆叠，其在衬底上具有第一栅极电介质，第一栅极电介质的介电常数高于二氧化硅的介电常数，以及金属材料 与第一栅极电介质接触，金属材料被掺杂惰性元素。 还提供了包括晶体管的集成电路和形成晶体管的方法。

公开(公告)号：US20110254129A1

公开(公告)日：2011-10-20

申请号：US13171320

申请日：2011-06-28

申请人： Rishikesh Krishnan ,  Dan Gealy ,  Vidya Srividya ,  Noel Rocklein

发明人： Rishikesh Krishnan ,  Dan Gealy ,  Vidya Srividya ,  Noel Rocklein

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01G4/255 ,  H01L27/10852 ,  H01L28/65

摘要： Electrical components for microelectronic devices and methods for forming electrical components. One particular embodiment of such a method comprises depositing an underlying layer onto a workpiece, and forming a conductive layer on the underlying layer. The method can continue by disposing a dielectric layer on the conductive layer. The underlying layer is a material that causes the dielectric layer to have a higher dielectric constant than without the underlying layer being present under the conductive layer. For example, the underlying layer can impart a structure or another property to the film stack that causes an otherwise amorphous dielectric layer to crystallize without having to undergo a separate high temperature annealing process after disposing the dielectric layer onto the conductive layer. Several examples of this method are expected to be very useful for forming dielectric layers with high dielectric constants because they avoid using a separate high temperature annealing process.

摘要翻译： 用于微电子器件的电气部件和用于形成电气部件的方法。 这种方法的一个具体实施方案包括将下面的层沉积到工件上，并在下层上形成导电层。 该方法可以通过在导电层上设置介电层来继续。 底层是导致电介质层具有比没有底层存在于导电层下方更高的介电常数的材料。 例如，下层可以赋予薄膜叠层的结构或另一性能，导致另外的非晶介质层结晶，而不必在将介电层设置在导电层上之后进行单独的高温退火工艺。 预期该方法的几个实例对于形成具有高介电常数的介电层非常有用，因为它们避免使用单独的高温退火工艺。

公开(公告)号：US20070264838A1

公开(公告)日：2007-11-15

申请号：US11431958

申请日：2006-05-10

申请人： Rishikesh Krishnan ,  Dan Gealy ,  Vidya Srividya ,  Noel Rocklein

发明人： Rishikesh Krishnan ,  Dan Gealy ,  Vidya Srividya ,  Noel Rocklein

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01G4/255 ,  H01L27/10852 ,  H01L28/65

摘要： Electrical components for microelectronic devices and methods for forming electrical components. One particular embodiment of such a method comprises depositing an underlying layer onto a workpiece, and forming a conductive layer on the underlying layer. The method can continue by disposing a dielectric layer on the conductive layer. The underlying layer is a material that causes the dielectric layer to have a higher dielectric constant than without the underlying layer being present under the conductive layer. For example, the underlying layer can impart a structure or another property to the film stack that causes an otherwise amorphous dielectric layer to crystallize without having to undergo a separate high temperature annealing process after disposing the dielectric layer onto the conductive layer. Several examples of this method are expected to be very useful for forming dielectric layers with high dielectric constants because they avoid using a separate high temperature annealing process.

摘要翻译： 用于微电子器件的电气部件和用于形成电气部件的方法。 这种方法的一个具体实施方案包括将下面的层沉积到工件上，并在下层上形成导电层。 该方法可以通过在导电层上设置介电层来继续。 底层是导致电介质层具有比没有底层存在于导电层下方更高的介电常数的材料。 例如，下层可以赋予薄膜叠层的结构或另一性能，导致另外的非晶介质层结晶，而不必在将介质层设置在导电层上之后进行单独的高温退火工艺。 预期该方法的几个实例对于形成具有高介电常数的介电层非常有用，因为它们避免使用单独的高温退火工艺。

公开(公告)号：US20070207588A1

公开(公告)日：2007-09-06

申请号：US11796773

申请日：2007-04-30

申请人： Cem Basceri ,  Vishnu Agarwal ,  Dan Gealy

发明人： Cem Basceri ,  Vishnu Agarwal ,  Dan Gealy

IPC分类号： H01L21/328 ,  H01L21/20

CPC分类号： H01L21/02183 ,  H01L21/02356 ,  H01L21/31637 ,  H01L27/10852 ,  H01L27/10855 ,  H01L28/65 ,  H01L28/91

摘要： Systems, devices, structures, and methods are described that inhibit dielectric degradation at high temperatures. An enhanced capacitor is discussed. The enhanced capacitor includes a first electrode, a dielectric that includes ditantalum pentaoxide, and a second electrode having a compound. The compound includes a first substance and a second substance. The second electrode includes a trace amount of the first substance. The morphology of the semiconductor structure remains stable when the trace amount of the first substance is oxidized during crystallization of the dielectric. In one embodiment, the crystalline structure of the dielectric describes substantially a (001) lattice plane.

公开(公告)号：US20070048953A1

公开(公告)日：2007-03-01

申请号：US11216542

申请日：2005-08-30

申请人： Dan Gealy ,  Vishwanath Bhat ,  Cancheepuram Srividya ,  M. Rocklein

发明人： Dan Gealy ,  Vishwanath Bhat ,  Cancheepuram Srividya ,  M. Rocklein

IPC分类号： H01L21/336

CPC分类号： H01L21/022 ,  C23C16/45529 ,  H01L21/02148 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/28194 ,  H01L21/3141 ,  H01L21/3142 ,  H01L21/31641 ,  H01L21/31645 ,  H01L28/40 ,  H01L28/56 ,  H01L29/517 ,  H01L29/78

摘要： Graded dielectric layers and methods of fabricating such dielectric layers provide dielectrics in a variety of electronic structures for use in a wide range of electronic devices and systems. In an embodiment, a dielectric layer is graded with respect to a doping profile across the dielectric layer. In an embodiment, a dielectric layer is graded with respect to a crystalline structure profile across the dielectric layer. In an embodiment, a dielectric layer is formed by atomic layer deposition incorporating sequencing techniques to generate a doped dielectric material.

摘要翻译： 梯度介电层和制造这种电介质层的方法在各种电子结构中提供电介质以用于广泛的电子设备和系统。 在一个实施例中，电介质层相对于跨介电层的掺杂分布而分级。 在一个实施例中，电介质层相对于介电层上的晶体结构分布呈梯度分布。 在一个实施例中，通过包含测序技术的原子层沉积形成电介质层以产生掺杂的电介质材料。

公开(公告)号：US20050032299A1

公开(公告)日：2005-02-10

申请号：US10931396

申请日：2004-08-31

申请人： Cem Basceri ,  Vishnu Agarwal ,  Dan Gealy

发明人： Cem Basceri ,  Vishnu Agarwal ,  Dan Gealy

IPC分类号： H01L21/02 ,  H01L21/316 ,  H01L21/8242 ,  H01L21/8234 ,  H01L21/8244 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L21/02183 ,  H01L21/02356 ,  H01L21/31637 ,  H01L27/10852 ,  H01L27/10855 ,  H01L28/65 ,  H01L28/91

摘要： Systems, devices, structures, and methods are described that inhibit dielectric degradation at high temperatures. An enhanced capacitor is discussed. The enhanced capacitor includes a first electrode, a dielectric that includes ditantalum pentaoxide, and a second electrode having a compound. The compound includes a first substance and a second substance. The second electrode includes a trace amount of the first substance. The morphology of the semiconductor structure remains stable when the trace amount of the first substance is oxidized during crystallization of the dielectric. In one embodiment, the crystalline structure of the dielectric describes substantially a (001) lattice plane.

摘要翻译： 描述了在高温下抑制电介质降解的系统，装置，结构和方法。 讨论了增强型电容器。 增强电容器包括第一电极，包括五氧化二钽的电介质和具有化合物的第二电极。 该化合物包括第一物质和第二物质。 第二电极包括痕量的第一物质。 当电介质结晶期间第一物质的痕量被氧化时，半导体结构的形态保持稳定。 在一个实施例中，电介质的晶体结构基本上描述了（001）晶格平面。

公开(公告)号：US20050019493A1

公开(公告)日：2005-01-27

申请号：US10925560

申请日：2004-08-25

申请人： Cem Basceri ,  Dan Gealy ,  Gurtej Sandhu

发明人： Cem Basceri ,  Dan Gealy ,  Gurtej Sandhu

IPC分类号： C23C16/40 ,  C23C16/52 ,  H01L21/314 ,  H01L21/316 ,  C23C16/00 ,  B05D5/12

CPC分类号： H01L21/02271 ,  C23C16/409 ,  C23C16/52 ,  H01L21/02197 ,  H01L21/31691

摘要： A method for controlling stoichiometry of dielectric films, e.g., BST films, preferably formed at low deposition temperatures. A deposition process may use an adjustment in oxidizer flow and/or partial pressure, the provision of a hydrogen-containing component, an adjustment in hydrogen-containing component flow and/or partial pressure, an adjustment in deposition pressure, and/or a modification of system component parameters (e.g., heating a shower head or adjusting a distance between a shower head of the deposition system and a wafer upon which the film is to be deposited), to control the characteristics of the dielectric film, e.g., film stoichiometry.