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    P-contact for GaN-based semiconductors utilizing a reverse-biased tunnel junction
    1.
    发明授权
    P-contact for GaN-based semiconductors utilizing a reverse-biased tunnel junction 有权
    利用反向偏置隧道结的GaN基半导体的P接触

    公开(公告)号：US06526082B1

    公开(公告)日：2003-02-25

    申请号：US09586406

    申请日：2000-06-02

    申请人： Scott W. Corzine ,  Richard P. Schneider, Jr. ,  Ghulam Hasnain

    发明人： Scott W. Corzine ,  Richard P. Schneider, Jr. ,  Ghulam Hasnain

    IPC分类号： H01S500

    CPC分类号： H01S5/10 ,  H01S5/32341 ,  H01S5/4037 ,  H01S2301/14

    摘要： A light-generating device such as a laser or LED. A light-generating device according to the present invention includes a first n-electrode layer in contact with a first n-contact layer, the first n-contact layer including an n-doped semiconductor. Light is generated by the recombination of holes and electrons in an n-p active layer. The n-p active layer includes a first p-doped layer in contact with a first n-doped layer, the first n-doped layer being connected electrically with the first n-contact layer. A p-n reverse-biased tunnel diode constructed from a second p-doped layer in contact with a second n-doped layer is connected electrically such that the second p-doped layer is connected electrically with the first p-layer. A second n-contact layer constructed from an n-doped semiconductor material is connected electrically to the second n-doped layer. A second n-electrode layer is placed in contact with the second n-contact layer. The various layers of the invention can be constructed from GaN semiconductors. The p-n reverse-biased tunnel diode includes an n-depletion region in the second n-doped layer and a p-depletion region in the second p-doped layer, the n-depletion region and the p-depletion region in contact with one another. The conductivity of the reverse-bias tunnel diode may be increased by doping the n-depletion region and p-depletion region. The conductivity of the reverse-bias tunnel diode can also be increased by including a compressively strained InGaN layer in the n-depletion region.

    摘要翻译： 诸如激光或LED的发光装置。 根据本发明的发光装置包括与第一n接触层接触的第一n电极层，第一n接触层包括n掺杂半导体。 光通过n-p活性层中空穴和电子的重组而产生。 n-p有源层包括与第一n掺杂层接触的第一p掺杂层，第一n掺杂层与第一n接触层电连接。 由与第二n掺杂层接触的第二p掺杂层构成的p-n反向偏置隧道二极电连接使得第二p掺杂层与第一p型掺杂层电连接。 由n掺杂半导体材料构成的第二n接触层与第二n掺杂层电连接。 第二n电极层被放置成与第二n接触层接触。 本发明的各个层可以由GaN半导体构成。 pn反向偏置隧道二极管包括第二n掺杂层中的n耗尽区和第二p掺杂层中的p耗尽区，n耗尽区和p耗尽区彼此接触 。 可以通过掺杂n耗尽区和p耗尽区来增加反向偏置隧道二极管的导电性。 反偏压隧道二极管的导电性也可以通过在n耗尽区域中包括压缩应变的InGaN层来增加。

    Epitaxial material grown laterally within a trench and method for producing same
    3.
    发明授权
    Epitaxial material grown laterally within a trench and method for producing same 失效
    在沟槽内横向生长的外延材料及其制造方法

    公开(公告)号：US06500257B1

    公开(公告)日：2002-12-31

    申请号：US09062028

    申请日：1998-04-17

    申请人： Shih-Yuan Wang ,  Changhua Chen ,  Yong Chen ,  Scott W. Corzine ,  R. Scott Kern ,  Richard P. Schneider, Jr.

    发明人： Shih-Yuan Wang ,  Changhua Chen ,  Yong Chen ,  Scott W. Corzine ,  R. Scott Kern ,  Richard P. Schneider, Jr.

    IPC分类号： C30B2300

    CPC分类号： H01L21/02647 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/0254 ,  H01L21/02642

    摘要： An epitaxial material grown laterally in a trench allows for the fabrication of a trench-based semiconductor material that is substantially low in dislocation density. Initiating the growth from a sidewall of a trench minimizes the density of dislocations present in the lattice growth template, which minimizes the dislocation density in the regrown material. Also, by allowing the regrowth to fill and overflow the trench, the low dislocation density material can cover the entire surface of the substrate upon which the low dislocation density material is grown. Furthermore, with successive iterations of the trench growth procedure, higher quality material can be obtained. Devices that require a stable, high quality epitaxial material can then be fabricated from the low dislocation density material.

    摘要翻译： 在沟槽中横向生长的外延材料允许制造基本上低的位错密度的基于沟槽的半导体材料。 从沟槽的侧壁开始生长使晶格生长模板中存在的位错的密度最小化，这使再生材料中的位错密度最小化。 此外，通过允许再生长填充和溢出沟槽，低位错密度材料可以覆盖生长低位错密度材料的基底的整个表面。 此外，随着沟槽生长过程的连续迭代，可以获得更高质量的材料。 然后可以从低位错密度材料制造需要稳定的高质量外延材料的器件。

    Near planar native-oxide VCSEL devices and arrays using converging oxide ringlets
    4.
    发明授权
    Near planar native-oxide VCSEL devices and arrays using converging oxide ringlets 失效
    近平面自然氧化物VCSEL器件和使用会聚氧化物小环的阵列

    公开(公告)号：US5896408A

    公开(公告)日：1999-04-20

    申请号：US911708

    申请日：1997-08-15

    申请人： Scott W. Corzine ,  Richard P. Schneider, Jr. ,  Michael R. T. Tan

    发明人： Scott W. Corzine ,  Richard P. Schneider, Jr. ,  Michael R. T. Tan

    IPC分类号： H01S5/00 ,  H01S5/183 ,  H01S5/42 ,  H01S3/19 ,  H01L21/20 ,  H01S3/08

    CPC分类号： H01S5/18313 ,  H01S5/2086 ,  H01S5/423

    摘要： A VCSEL with a near planar top surface on which the top electrode is deposited. A VCSEL according to the present invention includes a top electrode, a top mirror having a top surface, a light generation region, and a bottom mirror for reflecting light toward the top mirror. At least one of the mirrors includes a plurality of planar electrically conducting layers having different indices of refraction. In addition, at least one of the layers includes an oxidizable material. To expose this layer to an oxidizing agent (thereby converting the material to an electrical insulator), three or more holes are etched down from the top surface of the VCSEL to the layer containing the oxidizable material. The oxidizing agent is then introduced into the top of these holes. The partial oxidation of the layer converts the layer to one having a conducting region surrounded by an electrically insulating region, the conducting region being positioned under the top electrode.

    摘要翻译： 具有近平面顶表面的VCSEL，其上沉积有顶电极。 根据本发明的VCSEL包括顶电极，具有顶表面的上反射镜，光产生区域和用于向上反射镜反射光的底镜。 至少一个反射镜包括具有不同折射率的多个平面导电层。 此外，至少一层包括可氧化材料。 为了将该层暴露于氧化剂（从而将材料转化为电绝缘体），从VCSEL的顶表面向包含可氧化材料的层蚀刻三个或更多个孔。 然后将氧化剂引入这些孔的顶部。 该层的部分氧化将该层转变为具有由电绝缘区域包围的导电区域的层，该导电区域位于顶部电极之下。

    High intensity single-mode VCSELs
    5.
    发明授权
    High intensity single-mode VCSELs 失效
    高强度单模VCSEL

    公开(公告)号：US5838715A

    公开(公告)日：1998-11-17

    申请号：US667259

    申请日：1996-06-20

    申请人： Scott W. Corzine ,  Dubravko I. Babic ,  Richard P. Schneider, Jr. ,  Michael R. Tan ,  Shih-Yuan Wang

    发明人： Scott W. Corzine ,  Dubravko I. Babic ,  Richard P. Schneider, Jr. ,  Michael R. Tan ,  Shih-Yuan Wang

    IPC分类号： H01S5/00 ,  H01S5/183 ,  H01S3/08 ,  H01S3/19

    CPC分类号： H01S5/18388 ,  H01S2301/166 ,  H01S5/1089 ,  H01S5/18308 ,  H01S5/18327 ,  H01S5/18372 ,  H01S5/2063

    摘要： A VCSEL 101 comprising an optical cavity having an optical loss and a loss-determining element 117 coupled to the optical cavity. The loss-determining element 117 progressively increases the optical loss of the optical cavity with increasing lateral distance from the optical axis 105. The optical cavity includes a first mirror region 111, a second mirror region 107, a plane light-generating region 125 sandwiched between the first mirror region 111 and the second mirror region 107, perpendicular to the optical axis 105, and an element 113 that defines the lateral extent of the optical cavity in the plane of the light-generating region 125. The first mirror region 111 and the second mirror region 107 are both conductive and have opposite conductivity modes.

    摘要翻译： 包括具有光学损耗的光学腔和耦合到光腔的损耗确定元件117的VCSEL 101。 损耗确定元件117随着从光轴105的横向距离的增加而逐渐增加光学腔的光学损耗。光学腔包括第一镜面区域111，第二镜面区域107，夹在两者之间的平面光产生区域125 垂直于光轴105的第一镜面区域111和第二镜面区域107以及限定光产生区域125的平面中的光腔的横向范围的元件113.第一镜面区域111和 第二反射镜区域107都是导电的并具有相反的导电模式。

    Integrated circuit substrate that accommodates lattice mismatch stress
    8.
    发明授权
    Integrated circuit substrate that accommodates lattice mismatch stress 有权
    集成电路基板，适应晶格失配应力

    公开(公告)号：US06429466B2

    公开(公告)日：2002-08-06

    申请号：US09774199

    申请日：2001-01-29

    申请人： Yong Chen ,  Scott W. Corzine ,  Theodore I. Kamins ,  Michael J. Ludowise ,  Pierre H. Mertz ,  Shih-Yuan Wang

    发明人： Yong Chen ,  Scott W. Corzine ,  Theodore I. Kamins ,  Michael J. Ludowise ,  Pierre H. Mertz ,  Shih-Yuan Wang

    IPC分类号： H01L31072

    CPC分类号： H01L21/7624 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02538 ,  H01L21/0254 ,  H01L21/02658 ,  H01L21/26533

    摘要： A method for growing a crystalline layer that includes a first material on a growth surface of a crystalline substrate of a second material, wherein the first material and the second material have different lattice constants. A buried layer is generated in the substrate such that the buried layer isolates a layer of the substrate that includes the growth surface from the remainder of the substrate. The second material is then deposited on the growth surface at a growth temperature. The isolated layer of the substrate has a thickness that is less than the thickness at which defects are caused in the crystalline lattice of the first material by the second material crystallizing thereon. The buried layer is sufficiently malleable at the growth temperature to allow the deformation of the lattice of the isolated layer without deforming the remainder of the substrate. The present invention may be utilized for growing III-V semiconducting material layers on silicon substrates. In the case of silicon-based substrates, the buried layer is preferably SiO2 that is sufficiently malleable at the growth temperature to allow the deformation of the isolated substrate layer.

    摘要翻译： 一种用于生长晶体层的方法，其包括在第二材料的晶体衬底的生长表面上的第一材料，其中第一材料和第二材料具有不同的晶格常数。 在衬底中产生掩埋层，使得掩埋层将衬底的包含生长表面的衬底与衬底的其余部分隔离。 然后将第二种材料在生长温度下沉积在生长表面上。 衬底的隔离层的厚度小于在其上结晶第二材料时在第一材料的晶格中产生缺陷的厚度。 掩埋层在生长温度下具有足够的延展性，以允许隔离层的晶格变形，而不使基底的其余部分变形。 本发明可用于在硅衬底上生长III-V半导体材料层。 在硅基基板的情况下，掩埋层优选是在生长温度下足够有韧性的SiO 2，以允许隔离的基底层的变形。

    Buried heterostructure device having integrated waveguide grating fabricated by single step MOCVD
    9.
    发明授权
    Buried heterostructure device having integrated waveguide grating fabricated by single step MOCVD 失效
    具有通过单步MOCVD制造的集成波导光栅的埋入异质结构器件

    公开(公告)号：US07941024B2

    公开(公告)日：2011-05-10

    申请号：US12207521

    申请日：2008-09-10

    申请人： David P. Bour ,  Scott W. Corzine

    发明人： David P. Bour ,  Scott W. Corzine

    IPC分类号： G02B6/10

    CPC分类号： H01S5/12 ,  B82Y20/00 ,  G02B6/131 ,  H01S5/1231 ,  H01S5/1237 ,  H01S5/2004 ,  H01S5/2009 ,  H01S5/2201 ,  H01S5/2214 ,  H01S5/227 ,  H01S5/3211 ,  H01S5/34313 ,  H01S5/34366 ,  H01S2301/173 ,  H01S2304/04

    摘要： The device is an optoelectronic device or transparent waveguide device that comprises a growth surface, a growth mask, an optical waveguide core mesa and a cladding layer. The growth mask is located on the semiconductor surface and defines an elongate growth window having a periodic grating profile. The optical waveguide core mesa is located in the growth window and has a trapezoidal cross-sectional shape. The cladding layer covers the optical waveguide core mesa and extends over at least part of the growth mask. Such devices are fabricated by providing a wafer comprising a growth surface, growing an optical waveguide core mesa on the growth surface by micro-selective area growth at a first growth temperature and covering the optical waveguide core mesa with cladding material at a second growth temperature, lower than the first growth temperature.

    摘要翻译： 该器件是包括生长表面，生长掩模，光波导核心台面和包层的光电器件或透明波导器件。 生长掩模位于半导体表面上并且限定具有周期性光栅轮廓的细长生长窗口。 光波导核心台面位于生长窗口中，具有梯形横截面形状。 包覆层覆盖光波导芯体台面并在生长掩模的至少一部分上延伸。 这样的器件通过提供包括生长表面的晶片来制造，通过在第一生长温度下的微选择性区域生长在生长表面上生长光波导核心台面并且在第二生长温度下覆盖包含材料的光波导芯台面， 低于第一生长温度。