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    SALICIDATION PROCESS USING ELECTROLESS PLATING TO DEPOSIT METAL AND INTRODUCE DOPANT IMPURITIES
    1.
    发明申请
    SALICIDATION PROCESS USING ELECTROLESS PLATING TO DEPOSIT METAL AND INTRODUCE DOPANT IMPURITIES 审中-公开
    使用电沉积金属沉淀金属和引入D ANT IMP TIES TIES TIES TIES TIES TIES

    公开(公告)号：US20090004851A1

    公开(公告)日：2009-01-01

    申请号：US11770817

    申请日：2007-06-29

    申请人： Shau-Lin Shue ,  Ting-Chu Ko ,  Chien-Hsueh Shih

    发明人： Shau-Lin Shue ,  Ting-Chu Ko ,  Chien-Hsueh Shih

    IPC分类号： H01L21/02

    CPC分类号： H01L21/2254 ,  H01L21/28518 ,  H01L21/288

    摘要： A selective electroless plating operation provides for the selective deposition of a metal film only on exposed silicon surfaces of a semiconductor substrate and not on other surfaces such as dielectric surfaces. The plating solution includes metal ions and advantageously also includes dopant impurity ions. The pure metal or metal alloy film formed on the exposed silicon surfaces is then heat treated to form a metal silicide on the exposed silicon surfaces and to drive the dopant impurities to the interface formed between the exposed silicon surfaces and the metal silicide film.

    摘要翻译： 选择性化学镀操作提供仅在半导体衬底的暴露的硅表面上而不是在诸如电介质表面的其它表面上的金属膜的选择性沉积。 电镀溶液包括金属离子，并且有利地还包括掺杂剂杂质离子。 形成在暴露的硅表面上的纯金属或金属合金膜然后被热处理以在暴露的硅表面上形成金属硅化物，并将掺杂剂杂质驱动到形成在暴露的硅表面和金属硅化物膜之间的界面。

    Transitional interface between metal and dielectric in interconnect structures
    2.
    发明授权
    Transitional interface between metal and dielectric in interconnect structures 有权
    互连结构中金属和电介质之间的过渡界面

    公开(公告)号：US08349730B2

    公开(公告)日：2013-01-08

    申请号：US12823649

    申请日：2010-06-25

    申请人： Chien-Hsueh Shih ,  Shau-Lin Shue

    发明人： Chien-Hsueh Shih ,  Shau-Lin Shue

    IPC分类号： H01L21/44 ,  H01L23/52

    CPC分类号： H01L23/53238 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76858 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit structure and methods for forming the same are provided. The integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; an opening in the dielectric layer; a conductive line in the opening; a metal alloy layer overlying the conductive line; a first metal silicide layer overlying the metal alloy layer; and a second metal silicide layer different from the first metal silicide layer on the first metal silicide layer. The metal alloy layer and the first and the second metal silicide layers are substantially vertically aligned to the conductive line.

    摘要翻译： 提供一种集成电路结构及其形成方法。 集成电路结构包括半导体衬底; 半导体衬底上的电介质层; 电介质层中的开口; 开口中的导电线; 覆盖导线的金属合金层; 覆盖在金属合金层上的第一金属硅化物层; 以及与第一金属硅化物层上的第一金属硅化物层不同的第二金属硅化物层。 金属合金层和第一和第二金属硅化物层基本上垂直对准导电线。

    SEMICONDUCTOR INTERCONNECTION STRUCTURE AND METHOD FOR MAKING THE SAME
    4.
    发明申请
    SEMICONDUCTOR INTERCONNECTION STRUCTURE AND METHOD FOR MAKING THE SAME 审中-公开
    半导体互连结构及其制造方法

    公开(公告)号：US20090117731A1

    公开(公告)日：2009-05-07

    申请号：US11934005

    申请日：2007-11-01

    申请人： Chen-Hua Yu ,  Shau-Lin Shue ,  Chien-Hsueh Shih ,  Ming-Shih Yeh ,  Ming-Han Lee

    发明人： Chen-Hua Yu ,  Shau-Lin Shue ,  Chien-Hsueh Shih ,  Ming-Shih Yeh ,  Ming-Han Lee

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76844 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76877 ,  H01L2221/1089

    摘要： A semiconductor interconnection structure is manufactured as follows. First, a substrate with a first dielectric layer and a second dielectric layer is formed. Subsequently, an opening is formed in the second dielectric layer. A thin metal layer and a seed layer are formed in sequence on the surface of the second dielectric layer in the opening, wherein the metal layer comprises at least one metal species having phase segregation property of a second conductor. The wafer of the substrate is subjected to a thermal treatment, by which most of the metal species in the metal layer at a bottom of the opening is diffused to a top surface of the second conductor to form a metal-based oxide layer. Afterwards, the wafer is subjected to planarization, so as to remove the second conductor outside the opening.

    摘要翻译： 如下制造半导体互连结构。 首先，形成具有第一介电层和第二介质层的基板。 随后，在第二电介质层中形成开口。 在开口中的第二电介质层的表面上依次形成薄金属层和种子层，其中金属层包含至少一种具有第二导体的相分离特性的金属物质。 对基板的晶片进行热处理，通过该热处理，开口底部的金属层中的大部分金属物质扩散到第二导体的顶表面，形成金属基氧化物层。 然后，对晶片进行平面化处理，以便将开口外的第二导体移除。

    Ultra-low resistance interconnect
    5.
    发明申请
    Ultra-low resistance interconnect 审中-公开
    超低电阻互连

    公开(公告)号：US20080251919A1

    公开(公告)日：2008-10-16

    申请号：US11786527

    申请日：2007-04-12

    申请人： Chien-Hsueh Shih ,  Shau-Lin Shue

    发明人： Chien-Hsueh Shih ,  Shau-Lin Shue

    IPC分类号： H01L23/532

    CPC分类号： H01L21/76844 ,  H01L21/288

    摘要： A method for fabricating a semiconductor interconnect device. A preferred embodiment comprises forming a low-k or very low-k dielectric layer on a wafer substrate and forming a recess in the dielectric layer that exposes a region on the substrate to which electrical contact is desired. A barrier layer is formed by first forming an organic layer on the walls of the substrate, then forming a catalyst metal layer on the organic layer, and finally forming a barrier metal layer over the catalyst layer. The remainder of the recess formed in the dielectric layer is then filled with a conductive material such as copper that will function as the main electrical connector to the contact region on the substrate.

    摘要翻译： 一种半导体互连器件的制造方法。 优选实施例包括在晶片衬底上形成低k或非常低k电介质层，并在电介质层中形成露出需要电接触的衬底上的区域的凹槽。 通过首先在基板的壁上形成有机层，然后在有机层上形成催化剂金属层，最后在催化剂层上形成阻挡金属层，形成阻挡层。 然后在电介质层中形成的凹部的其余部分用诸如铜的导电材料填充，该导电材料将用作基板上的接触区域的主要电连接器。

    Passivation structure for semiconductor devices
    6.
    发明申请
    Passivation structure for semiconductor devices 审中-公开
    半导体器件钝化结构

    公开(公告)号：US20060138668A1

    公开(公告)日：2006-06-29

    申请号：US11023296

    申请日：2004-12-27

    申请人： Hung-Wen Su ,  Chien-Hsueh Shih ,  Minghsing Tsai ,  Shau-Lin Shue ,  Chen-Hua Yu

    发明人： Hung-Wen Su ,  Chien-Hsueh Shih ,  Minghsing Tsai ,  Shau-Lin Shue ,  Chen-Hua Yu

    IPC分类号： H01L23/06

    CPC分类号： H01L23/53238 ,  H01L21/288 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76865 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A system and method for providing a passivation structure for semiconductor devices is provided. In an embodiment, the passivation structure comprises a first barrier layer and a second barrier layer, wherein the second barrier layer may comprise a material, such as cobalt and/or nickel, that is less pure than the first barrier layer. In another embodiment, a single gradient barrier layer is formed. In this embodiment the single gradient barrier layer exhibits a greater pure conductive material, such as cobalt and/or nickel, nearer the conductive line than near the surface.

    摘要翻译： 提供了一种用于提供半导体器件的钝化结构的系统和方法。 在一个实施例中，钝化结构包括第一阻挡层和第二阻挡层，其中第二阻挡层可以包括比第一阻挡层更纯的材料，例如钴和/或镍。 在另一个实施例中，形成单个梯度阻挡层。 在该实施例中，单个梯度阻挡层表现出比在表面附近更靠近导电线的较高纯度的导电材料，例如钴和/或镍。

    Transitional Interface Between Metal and Dielectric in Interconnect Structures
    7.
    发明申请
    Transitional Interface Between Metal and Dielectric in Interconnect Structures 有权
    互连结构中金属与介质之间的过渡接口

    公开(公告)号：US20100267232A1

    公开(公告)日：2010-10-21

    申请号：US12823649

    申请日：2010-06-25

    申请人： Chien-Hsueh Shih ,  Shau-Lin Shue

    发明人： Chien-Hsueh Shih ,  Shau-Lin Shue

    IPC分类号： H01L21/768

    CPC分类号： H01L23/53238 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76858 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit structure and methods for forming the same are provided. The integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; an opening in the dielectric layer; a conductive line in the opening; a metal alloy layer overlying the conductive line; a first metal silicide layer overlying the metal alloy layer; and a second metal silicide layer different from the first metal silicide layer on the first metal silicide layer. The metal alloy layer and the first and the second metal silicide layers are substantially vertically aligned to the conductive line.

    摘要翻译： 提供一种集成电路结构及其形成方法。 集成电路结构包括半导体衬底; 半导体衬底上的电介质层; 电介质层中的开口; 开口中的导电线; 覆盖导线的金属合金层; 覆盖在金属合金层上的第一金属硅化物层; 以及与第一金属硅化物层上的第一金属硅化物层不同的第二金属硅化物层。 金属合金层和第一和第二金属硅化物层基本上垂直对准导电线。

    Transitional interface between metal and dielectric in interconnect structures
    8.
    发明授权
    Transitional interface between metal and dielectric in interconnect structures 有权
    互连结构中金属和电介质之间的过渡界面

    公开(公告)号：US07777344B2

    公开(公告)日：2010-08-17

    申请号：US11786241

    申请日：2007-04-11

    申请人： Chien-Hsueh Shih ,  Shau-Lin Shue

    发明人： Chien-Hsueh Shih ,  Shau-Lin Shue

    IPC分类号： H01L23/52

    CPC分类号： H01L23/53238 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76858 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit structure and methods for forming the same are provided. The integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; an opening in the dielectric layer; a conductive line in the opening; a metal alloy layer overlying the conductive line; a first metal silicide layer overlying the metal alloy layer; and a second metal silicide layer different from the first metal silicide layer on the first metal silicide layer. The metal alloy layer and the first and the second metal silicide layers are substantially vertically aligned to the conductive line.

    摘要翻译： 提供一种集成电路结构及其形成方法。 集成电路结构包括半导体衬底; 半导体衬底上的电介质层; 电介质层中的开口; 开口中的导电线; 覆盖导线的金属合金层; 覆盖在金属合金层上的第一金属硅化物层; 以及与第一金属硅化物层上的第一金属硅化物层不同的第二金属硅化物层。 金属合金层和第一和第二金属硅化物层基本上垂直对准导电线。