公开(公告)号：US5594279A

公开(公告)日：1997-01-14

申请号：US149876

申请日：1993-11-10

申请人： Yutaka Itou ,  Hidetoshi Iwai ,  Toshiyuki Sakuta ,  Takumi Nasu ,  Tomohiro Suzuki

发明人： Yutaka Itou ,  Hidetoshi Iwai ,  Toshiyuki Sakuta ,  Takumi Nasu ,  Tomohiro Suzuki

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L23/522 ,  H01L23/552 ,  H01L23/48

CPC分类号： H01L24/06 ,  H01L23/5225 ,  H01L23/552 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/06136 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/4826 ,  H01L2224/48464 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025

摘要： A semiconductor device in which shield wiring is arranged between the semiconductor substrate and the power source wiring for supplying the power source potential or ground potential. Noise, as represented by variations in the potential of the semiconductor substrate, is substantially prevented from transferring to the aforementioned power source wiring by the shield wiring. In one aspect, shield wiring 1 is arranged between Vss wiring for supplying potential to the various circuits on the semiconductor substrate and substrate 7. This shield wiring 1 is connected to grounding lead frame 18 via M1 intra-chip wiring 4, M2 intra-chip wiring 5, connecting part 40, bonding pad 3 and bonding wire 8. Since the coupling impedance between shield wiring 1 and substrate 7 (due almost solely to the electrostatic capacitance Css) is large, and coupling impedance between Vss wiring 2 and substrate 7 (due almost solely to the junction capacitance D) is low, the noise caused by variations in the potential of substrate 7 is transferred to shield wiring 1, while it is not appreciably transferred to Vss wiring 2.

摘要翻译： 一种半导体器件，其中屏蔽布线布置在半导体衬底和用于提供电源电位或接地电位的电源布线之间。 基本上防止了由半导体衬底的电位变化所表示的噪声通过屏蔽布线转移到上述电源布线。 在一个方面，屏蔽布线1布置在用于向半导体衬底和衬底7上的各种电路供电的Vss布线之间。该屏蔽布线1经由M1片内布线4，M2片内连接到接地引线框架18 布线5，连接部40，接合焊盘3和接合线8.由于屏蔽布线1和基板7之间的耦合阻抗（几乎完全相当于静电电容Css），所以Vss布线2和基板7 由于几乎完全由结电容D）导致的，基板7的电位的变化引起的噪声被传送到屏蔽布线1，而不明显地转移到Vss布线2。

公开(公告)号：US5689465A

公开(公告)日：1997-11-18

申请号：US703178

申请日：1996-08-26

申请人： Shunichi Sukegawa ,  Takumi Nasu ,  Hidetoshi Iwai

发明人： Shunichi Sukegawa ,  Takumi Nasu ,  Hidetoshi Iwai

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/78 ,  G11C29/785 ,  G11C29/84 ,  G11C29/781

摘要： To provide a semiconductor memory device characterized by the fact that it can prevent errors in the redundant memory address coincidence signal generating circuit caused by the intrinsic resistance of the fuse in the fuse decoder, and it has a redundant mechanism for generating the high-speed address coincidence signal. It has multiple logic gate means and fuses programmable by the gate output. The output signal of each fuse is wired to generate address coincidence signal.

摘要翻译： 提供一种半导体存储器件，其特征在于它可以防止由熔丝解码器中的熔丝的固有电阻引起的冗余存储器地址一致信号产生电路中的错误，并且它具有用于产生高速地址的冗余机制 巧合信号。 它具有由门输出可编程的多个逻辑门装置和保险丝。 每个保险丝的输出信号被连线以产生地址一致信号。

公开(公告)号：US5550394A

公开(公告)日：1996-08-27

申请号：US80159

申请日：1993-06-18

申请人： Shunichi Sukegawa ,  Takumi Nasu ,  Hidetoshi Iwai

发明人： Shunichi Sukegawa ,  Takumi Nasu ,  Hidetoshi Iwai

IPC分类号： G11C29/00 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： G11C29/78 ,  G11C29/785 ,  G11C29/84 ,  G11C29/781

摘要： To provide a semiconductor memory device characterized by the fact that it can prevent errors in the redundant memory address coincidence signal generating circuit caused by the intrinsic resistance of the fuse in the fuse decoder, and it has a redundant mechanism for generating the high-speed address coincidence signal. It has multiple logic gate means and fuses programmable by the gate output. The output signal of each fuse is wired to generate address coincidence signal.

摘要翻译： 提供一种半导体存储器件，其特征在于它可以防止由熔丝解码器中的熔丝的固有电阻引起的冗余存储器地址一致信号产生电路中的错误，并且它具有用于产生高速地址的冗余机制 巧合信号。 它具有由门输出可编程的多个逻辑门装置和保险丝。 每个保险丝的输出信号被连线以产生地址一致信号。

公开(公告)号：US5208782A

公开(公告)日：1993-05-04

申请号：US892708

申请日：1992-05-29

申请人： Toshiyuki Sakuta ,  Masamichi Ishihara ,  Kazuyuki Miyazawa ,  Masanori Tazunoki ,  Hidetoshi Iwai ,  Hisashi Nakamura ,  Yasushi Takahashi ,  Toshio Maeda ,  Hiromi Matsuura ,  Ryoichi Hori ,  Toshio Sasaki ,  Osamu Sakai ,  Hiroyuki Uchiyama ,  Eiji Miyamoto ,  Kazuyoshi Oshima ,  Yasuhiro Kasama

发明人： Toshiyuki Sakuta ,  Masamichi Ishihara ,  Kazuyuki Miyazawa ,  Masanori Tazunoki ,  Hidetoshi Iwai ,  Hisashi Nakamura ,  Yasushi Takahashi ,  Toshio Maeda ,  Hiromi Matsuura ,  Ryoichi Hori ,  Toshio Sasaki ,  Osamu Sakai ,  Hiroyuki Uchiyama ,  Eiji Miyamoto ,  Kazuyoshi Oshima ,  Yasuhiro Kasama

IPC分类号： G06F11/18 ,  G06F11/20 ,  G11C11/406 ,  G11C29/00 ,  H01L27/105 ,  H01L27/108

CPC分类号： G11C29/808 ,  G11C11/406 ,  G11C29/88 ,  H01L24/06 ,  H01L27/10805 ,  G06F11/1666 ,  G06F11/183 ,  H01L2224/4826 ,  H01L27/105 ,  H01L2924/13091 ,  H01L2924/14

摘要： A semiconductor integrated circuit memory structure is provided which uses macro-cellulated circuit blocks that can permit a very large storage capability (for example, on the order of 64 Mbits in a DRAM) on a single chip. To achieve, this, a plurality of macro-cellulated memory blocks can be provided, with each of the memory blocks including a memory array as well as additional circuitry such as address selection circuits and input/output circuits. Other peripheral circuits are provided on the chip which are common to the plurality of macro-cell memory blocks. The macro-cell memory blocks themselves can be formed in an array so that their combined storage capacity will form the large overall storage capacity of the chip. The combination of the macro-cell memory blocks and the common peripheral circuitry for controlling the memory blocks permits a faster and more efficient refreshing operation for a DRAM. This is enhanced by a LOC (Lead On Chip) arrangement used in conjunction with the memory blocks.

摘要翻译： 提供了一种半导体集成电路存储器结构，其使用宏单元电路块，其可以在单个芯片上允许非常大的存储能力（例如，DRAM中的64Mbits）。 为了实现这一点，可以提供多个宏单元存储器块，其中每个存储器块包括存储器阵列以及诸如地址选择电路和输入/输出电路的附加电路。 在芯片上提供了多个宏单元存储块通用的其他外围电路。 宏单元存储器块本身可以形成为阵列，使得它们的组合存储容量将形成芯片的大的总体存储容量。 宏单元存储器块和用于控制存储器块的公共外围电路的组合允许DRAM的更快更有效的刷新操作。 这通过与存储器块结合使用的LOC（片上芯片）布置来增强。

公开(公告)号：US5410507A

公开(公告)日：1995-04-25

申请号：US977212

申请日：1992-11-16

申请人： Masanori Tazunoki ,  Shigetoshi Sakomura ,  Toshitsugu Takekuma ,  Yutaka Ito ,  Kazuya Ito ,  Wataru Arakawa ,  Hidetoshi Iwai ,  Toshiyuki Sakuta ,  Masamichi Ishihara

发明人： Masanori Tazunoki ,  Shigetoshi Sakomura ,  Toshitsugu Takekuma ,  Yutaka Ito ,  Kazuya Ito ,  Wataru Arakawa ,  Hidetoshi Iwai ,  Toshiyuki Sakuta ,  Masamichi Ishihara

IPC分类号： G11C11/4074 ,  G11C11/4076 ,  G11C13/00

CPC分类号： G11C11/4076 ,  G11C11/4074

摘要： A dynamic RAM provided with a data retention mode intended for low power consumption is provided. In the data retention mode, the current supply capabilities of voltage generation circuits which generate decreased voltage, increased voltage, reference voltage, etc., are limited in the range in which information retention operation in memory cells can be maintained, and the number of selected memory mats in the data retention mode is increased with respect to that of memory mats selected in the normal read/write mode and refresh mode. Special modes such as the data retention mode are set by combining an address strobe signal and other control signals and dummy CBR refresh is executed to release the special mode.

摘要翻译： 提供了具有旨在低功耗的数据保留模式的动态RAM。 在数据保持模式下，产生电压降低，电压升高，参考电压等的电压产生电路的电流供应能力在保持存储器单元的信息保持操作的范围内被限制，并且所选择的数量 相对于在正常读/写模式和刷新模式中选择的存储器垫，数据保持模式中的存储器垫增加。 通过组合地址选通信号和其他控制信号来设置数据保持模式等特殊模式，执行虚拟CBR刷新以释放特殊模式。

公开(公告)号：US5485425A

公开(公告)日：1996-01-16

申请号：US375727

申请日：1995-01-20

申请人： Hidetoshi Iwai ,  Masaya Muranaka ,  Takumi Nasu ,  Shunichi Sukegawa

发明人： Hidetoshi Iwai ,  Masaya Muranaka ,  Takumi Nasu ,  Shunichi Sukegawa

IPC分类号： G11C11/401 ,  G11C17/12 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C17/126 ,  G11C29/84

摘要： There is provided a semiconductor memory device having a redundant column. This memory device has a redundant column disposed in the direction of the Y-system address, a ROM accessed by using an X-system address, a Y-system address signal having a defective cell included in the cells therein being electrically written into the ROM, a comparator circuit for comparing a signal read out from this ROM with a Y-system address signal and outputting a coincidence signal upon coincidence, and a defect relieving circuit responsive to output of the coincidence signal from this comparator circuit to cause selection of the redundant column of Y system instead of the Y-system address selection device.

摘要翻译： 提供了具有冗余列的半导体存储器件。 该存储装置具有沿Y系统地址的方向设置的冗余列，通过使用X系统地址访问的ROM，其中包含在其中的单元中的具有缺陷单元的Y系统地址信号被电写入ROM 比较电路，用于将从该ROM读出的信号与Y系统地址信号进行比较，并且一致地输出一致信号，以及响应来自该比较器电路的符合信号的输出的缺陷消除电路，以选择冗余 Y系列的列，而不是Y系统地址选择设备。

公开(公告)号：US5359561A

公开(公告)日：1994-10-25

申请号：US872958

申请日：1992-04-23

申请人： Shigetoshi Sakomura ,  Kazuya Ito ,  Hidetoshi Iwai ,  Toshiyuki Sakuta ,  Masamichi Ishihara ,  Tomoshi Matsumoto, deceased

发明人： Shigetoshi Sakomura ,  Kazuya Ito ,  Hidetoshi Iwai ,  Toshiyuki Sakuta ,  Masamichi Ishihara ,  Tomoshi Matsumoto, deceased

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C29/24 ,  G11C7/00

CPC分类号： G11C29/24

摘要： A semiconductor memory device is provided which includes a plurality of data lines, at least one redundant data line, one common data line, a plurality of column switches installed between the plurality of data lines and the redundant data line and one common data line, and a column decoder for controlling the plurality of column switches. The column decoder operates to turn the column switch on. The column switch is connected to a plurality of data lines, excluding any defective data and redundant data lines during the test mode state.

摘要翻译： 提供一种半导体存储器件，其包括多个数据线，至少一个冗余数据线，一个公共数据线，安装在多个数据线与冗余数据线和一条公共数据线之间的多个列开关，以及 用于控制多个列开关的列解码器。 列解码器操作以打开列开关。 列开关连接到多个数据线，在测试模式状态期间不包括任何有缺陷的数据和冗余数据线。

公开(公告)号：US5629898A

公开(公告)日：1997-05-13

申请号：US607977

申请日：1996-02-29

申请人： Youji Idei ,  Katsuhiro Shimohigashi ,  Masakazu Aoki ,  Hiromasa Noda ,  Katsuyuki Sato ,  Hidetoshi Iwai ,  Makoto Saeki ,  Jun Murata ,  Yoshitaka Tadaki ,  Toshihiro Sekiguchi ,  Osamu Tsuchiya

发明人： Youji Idei ,  Katsuhiro Shimohigashi ,  Masakazu Aoki ,  Hiromasa Noda ,  Katsuyuki Sato ,  Hidetoshi Iwai ,  Makoto Saeki ,  Jun Murata ,  Yoshitaka Tadaki ,  Toshihiro Sekiguchi ,  Osamu Tsuchiya

IPC分类号： G11C11/406 ,  G11C11/407 ,  G11C7/00

CPC分类号： G11C11/406 ,  G11C2211/4016 ,  G11C2211/4061

摘要： A period pulse corresponding to the shortest information retention time of those of dynamic memory cells is counted to form a refresh address to be assigned to a plurality of word lines. A carry signal outputted from the refresh address counter is divided by a divider. For each of said plurality of word lines assigned with the refresh address, one of a short period corresponding to an output pulse of a timer or a long period corresponding to the divided pulse from the divider is stored in a storage circuit as refresh time setting information. A memory cell refresh operation to be performed by the refresh address is made valid or invalid for each word line according to the refresh time setting information stored in the storage circuit and the refresh time setting information itself is made invalid by the output pulse of the divider.

摘要翻译： 对与动态存储单元的最短信息保持时间对应的周期脉冲进行计数，以形成分配给多个字线的刷新地址。 从刷新地址计数器输出的进位信号由分频器分频。 对于分配有刷新地址的所述多个字线中的每一个，对应于定时器的输出脉冲的短周期中的一个或与来自分频器的分频脉冲相对应的长周期中的一个作为刷新时间设置信息被存储在存储电路中 。 根据存储在存储电路中的刷新时间设定信息，由刷新地址执行的存储器单元刷新动作对每个字线进行有效或无效，并且刷新时间设定信息本身被分频器的输出脉冲无效 。

公开(公告)号：US5458998A

公开(公告)日：1995-10-17

申请号：US886403

申请日：1992-05-21

申请人： Toshitsugu Takekuma ,  Toshio Suzuki ,  Hidetoshi Iwai ,  Masamichi Ishihara

发明人： Toshitsugu Takekuma ,  Toshio Suzuki ,  Hidetoshi Iwai ,  Masamichi Ishihara

IPC分类号： G03F1/00 ,  G03F1/26 ,  G03F1/30 ,  G03F1/36 ,  G03F1/68 ,  G03F1/84 ,  H01L21/027 ,  H01L21/30 ,  G03F9/00

CPC分类号： G03F1/26 ,  G03F1/29 ,  G03F1/84

摘要： Pattern data of a phase shift mask can be inspected: (101) by separating and laying out pattern data of a phase shift mask in an actual pattern data layer, an auxiliary pattern data layer and a phase shift pattern data layer; (102) by inspecting and correcting only the data of the actual pattern of the actual pattern data layer; (108) by making data of an estimated pattern estimated to be transferred to a semiconductor wafer from the data of the synthetic data of the correct actual pattern data, the auxiliary pattern data and the phase shift pattern data, which are inspected and corrected; and (104) by comparing the estimated pattern data and the actual pattern data to inspect the data of the auxiliary pattern and the phase shift pattern.

摘要翻译： 可以检查相移掩模的图案数据：（101）通过在实际图案数据层，辅助图案数据层和相移图案数据层中分离和布置相移掩模的图案数据; （102），通过检查和校正实际图案数据层的实际图案的数据; （108）通过从被检查和校正的正确的实际图案数据，辅助图案数据和相移图案数据的合成数据的数据中制作估计传送到半导体晶片的估计图案的数据; 和（104）通过比较估计的图案数据和实际图案数据来检查辅助图案和相移图案的数据。

公开(公告)号：US5287000A

公开(公告)日：1994-02-15

申请号：US674969

申请日：1991-03-26

申请人： Yasushi Takahashi ,  Kazuyuki Miyazawa ,  Hidetoshi Iwai ,  Masaya Muranaka ,  Yoshitaka Kinoshita ,  Satoru Koshiba

发明人： Yasushi Takahashi ,  Kazuyuki Miyazawa ,  Hidetoshi Iwai ,  Masaya Muranaka ,  Yoshitaka Kinoshita ,  Satoru Koshiba

IPC分类号： H01L23/495 ,  H01L23/48 ,  H01L27/10 ,  H01L29/44 ,  H02G3/08

CPC分类号： H01L24/06 ,  H01L23/4951 ,  H01L23/49541 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/48799 ,  H01L2224/49171 ,  H01L2224/49179 ,  H01L2224/73265 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12036 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011

摘要： According to one aspect of the present invention, a semiconductor chip, which can be mounted in a zigzag in-line type package (ZIP) partially using a tabless lead frame, includes bonding pads arranged on the chip so that the chip can be applied also to other different types of packages. These different types of packages include a small out-line J-bent type package (SOJ) which uses a lead frame with tab, and a dual in-line type package (DIP) which uses a tabless lead frame. Further, a plurality of bonding pad pairs are provided amongst the bonding pads on the chip, each pad of such bonding pad pairs having the same function as the other pad associated therewith thereby duplicating a common function in different bonding pads on the semiconductor chip so as to make the semiconductor chip compatible with a variety of or different types of packages. In accordance with another aspect of the invention, a resin-encapsulated semiconductor device of the ZIP structure is provided in which a semiconductor pellet having a plurality of external terminals disposed on a device-forming surface along each side of the planar shape is encapsulated with a resin, wherein inner leads for signals connected electrically with external terminals, disposed opposing to the surface of the resin-encapsulated portion disposed with outer leads and disposed along the most remote side of the semiconductor pellet, are arranged so as to overlap the semiconductor pellet.

摘要翻译： 根据本发明的一个方面，可以使用无引线引线框架部分地以锯齿形的在线型封装（ZIP）安装的半导体芯片包括布置在芯片上的焊盘，使得芯片也可以被应用 到其他不同类型的包。 这些不同类型的封装包括使用带引脚的引线框架的小型外部J型弯曲型封装（SOJ）和使用无引脚引线框架的双列直插型封装（DIP）。 此外，在芯片上的接合焊盘之间设置多个接合焊盘对，这种接合焊盘对的每个焊盘具有与其相关联的另一个焊盘相同的功能，从而在半导体芯片上的不同接合焊盘中复制共同的功能，以便 使半导体芯片与各种或不同类型的封装兼容。 根据本发明的另一方面，提供了一种ZIP结构的树脂封装的半导体器件，其中具有设置在沿着平面形状的每一侧的器件形成表面上的多个外部端子的半导体芯片被封装在 树脂，其中与外部端子电连接的信号的内部引线设置成与设置有外部引线并沿着半导体芯片的最远侧设置的树脂封装部分的表面相对设置，以与半导体芯片重叠。