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    Multilayered Wiring Substrate
    1.
    发明申请
    Multilayered Wiring Substrate 失效
    多层接线基板

    公开(公告)号：US20110156272A1

    公开(公告)日：2011-06-30

    申请号：US12976427

    申请日：2010-12-22

    申请人： Shinnosuke MAEDA ,  Tetsuo SUZUKI ,  Atsuhiko SUGIMOTO ,  Tatsuya ITO ,  Takuya HANDO ,  Satoshi HIRANO

    发明人： Shinnosuke MAEDA ,  Tetsuo SUZUKI ,  Atsuhiko SUGIMOTO ,  Tatsuya ITO ,  Takuya HANDO ,  Satoshi HIRANO

    IPC分类号： H01L23/48

    CPC分类号： H05K3/3452 ,  H01L23/49811 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K1/113 ,  H05K3/205 ,  H05K3/383 ,  H05K3/4682 ,  H05K2201/068 ,  H05K2201/094 ,  H05K2201/09527 ,  H05K2201/099 ,  H05K2203/0346 ,  H05K2203/0369 ,  H01L2924/00

    摘要： A multilayered wiring substrate, comprising: a plurality of first main surface side connecting terminals arranged in a first main surface of a stack structure; and a plurality of second main surface side connecting terminals being arranged in a second main surface of the stack structure; wherein a plurality of conductor layers are alternately formed in a plurality of stacked resin insulation layers and are operably connected to each other through via conductors tapered such that diameters thereof are widened toward the first or the second main surface, wherein a plurality of openings are formed in an exposed outermost resin insulation layer in the second main surface, and terminal outer surfaces of the second main surface side connecting terminals arranged to match with the plurality of the openings are positioned inwardly from an outer main surface of the exposed outermost resin insulation layer, and edges of terminal inner surfaces are rounded.

    摘要翻译： 一种多层布线基板，包括：布置在堆叠结构的第一主表面中的多个第一主表面侧连接端子; 并且多个第二主表面侧连接端子布置在所述堆叠结构的第二主表面中; 其中多个导体层交替地形成在多个堆叠的树脂绝缘层中，并且通过锥形的通孔导体可操作地连接，使得其直径朝向第一或第二主表面加宽，其中形成多个开口 在第二主表面中暴露的最外层树脂绝缘层中，并且布置成与多个开口相匹配的第二主表面侧连接端子的端子外表面从暴露的最外层树脂绝缘层的外主表面位于内侧， 并且端子内表面的边缘是圆形的。

    Multilayer Wiring Substrate
    2.
    发明申请
    Multilayer Wiring Substrate 审中-公开
    多层接线基板

    公开(公告)号：US20110155438A1

    公开(公告)日：2011-06-30

    申请号：US12978750

    申请日：2010-12-27

    申请人： Tatsuya ITO ,  Tetsuo SUZUKI ,  Takuya HANDO ,  Shinnosuke MAEDA ,  Atsuhiko SUGIMOTO ,  Satoshi HIRANO

    发明人： Tatsuya ITO ,  Tetsuo SUZUKI ,  Takuya HANDO ,  Shinnosuke MAEDA ,  Atsuhiko SUGIMOTO ,  Satoshi HIRANO

    IPC分类号： H05K1/11

    CPC分类号： H05K3/4682 ,  H05K1/113 ,  H05K3/4007 ,  H05K2201/094 ,  H05K2201/09427 ,  H05K2201/09472

    摘要： A multilayer wiring substrate has a multilayer wiring laminate portion in which a plurality of resin insulation layers made primarily of the same resin insulation material, and a plurality of conductive layers are laminated alternately. A plurality of first-main-surface-side connection terminals are disposed on one side of the laminate structure where a first main surface thereof is present, and a plurality of second-main-surface-side connection terminals being disposed on an other side of the laminate structure where a second main surface thereof is present. The plurality of conductive layers are formed in the plurality of resin insulation layers and interconnected by means of via conductors whose diameters increase toward the first main surface or the second main surface. The plurality of first-main-surface-side connection terminals comprising at least two types of terminals for connection of different articles-to-be-connected. Top surfaces of the plurality of first-main-surface-side connection terminals differ in height according to types of the articles-to-be-connected.

    摘要翻译： 多层布线基板具有多层布线层叠部，其中主要由相同树脂绝缘材料制成的多个树脂绝缘层和多个导电层交替层叠。 多个第一主表面侧连接端子设置在层叠结构的存在第一主表面的一侧上，并且多个第二主表面侧连接端子设置在 其中存在第二主表面的层压结构。 多个导电层形成在多个树脂绝缘层中，并且通过直径朝向第一主表面或第二主表面增大的通孔导体互连。 多个第一主表面侧连接端子包括用于连接不同待连接物品的至少两种类型的端子。 多个第一主表面侧连接端子的顶表面根据要连接的物品的类型而不同。

    Method of Manufacturing Multilayer Wiring Substrate, and Multilayer Wiring Substrate
    4.
    发明申请
    Method of Manufacturing Multilayer Wiring Substrate, and Multilayer Wiring Substrate 有权
    制造多层接线基板和多层接线基板的方法

    公开(公告)号：US20110200788A1

    公开(公告)日：2011-08-18

    申请号：US13028588

    申请日：2011-02-16

    申请人： Shinnosuke MAEDA ,  Tetsuo SUZUKI ,  Satoshi HIRANO

    发明人： Shinnosuke MAEDA ,  Tetsuo SUZUKI ,  Satoshi HIRANO

    IPC分类号： B32B3/24 ,  H05K3/06

    CPC分类号： H05K3/4682 ,  H05K1/112 ,  H05K3/205 ,  H05K2201/094 ,  H05K2201/09472 ,  H05K2201/099 ,  Y10T428/24331 ,  Y10T428/24339

    摘要： A plurality of openings are formed in a resin insulation layer on a bottom surface side of a wiring laminate portion which constitutes a multilayer wiring substrate. A plurality of motherboard connection terminals are disposed to correspond to the openings. The motherboard connection terminals are primarily comprised of a copper layer, and peripheral portions of terminal outer surfaces thereof are covered by the outermost resin insulation layer. A dissimilar metal layer made of at least one metal which is lower in etching rate than copper is formed between an inner main surface of the outermost resin insulation layer and peripheral portions of the terminal outer surfaces.

    摘要翻译： 在构成多层布线基板的布线层叠体的底面侧的树脂绝缘层上形成有多个开口部。 多个主板连接端子被设置成对应于这些开口。 母板连接端子主要由铜层构成，其端子外表面的周边部分被最外层树脂绝缘层覆盖。 在最外层树脂绝缘层的内主表面和端子外表面的周边部分之间形成由蚀刻速率低于铜的至少一种金属制成的异种金属层。

    Multilayer Wiring Substrate and Method of Manufacturing the Same
    5.
    发明申请
    Multilayer Wiring Substrate and Method of Manufacturing the Same 失效
    多层接线基板及其制造方法

    公开(公告)号：US20110211320A1

    公开(公告)日：2011-09-01

    申请号：US13031735

    申请日：2011-02-22

    申请人： Shinnosuke MAEDA ,  Takuya TORII ,  Tetsuo SUZUKI ,  Satoshi HIRANO

    发明人： Shinnosuke MAEDA ,  Takuya TORII ,  Tetsuo SUZUKI ,  Satoshi HIRANO

    IPC分类号： H05K7/00 ,  H05K3/36

    CPC分类号： H01L21/6835 ,  H01L23/3107 ,  H01L23/49811 ,  H01L23/49822 ,  H01L2221/68345 ,  H01L2924/0002 ,  H01L2924/19041 ,  H05K3/244 ,  H05K3/4682 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

    摘要： A multilayer wiring substrate includes first principal surface side connection terminals arranged on a first principal surface of a stacked configuration; wherein, the first principal surface side connection terminals include an IC chip connection terminal, and a passive element connection terminal; the IC chip connection terminal is located in an opening formed in a resin insulating layer of an uppermost outer layer; the passive element connection terminal is formed of an upper terminal part formed on the resin insulating layer, and a lower terminal part located in an opening formed at a portion of an inner side of the upper terminal part in the resin insulating layer; and, wherein an upper face of the upper terminal part is higher than a reference surface, and an upper face of the IC chip connection terminal and the lower terminal part are identical in height to or lower in height than the reference surface.

    摘要翻译： 多层布线基板包括布置在堆叠构造的第一主表面上的第一主表面侧连接端子; 其中，所述第一主面侧连接端子包括IC芯片连接端子和无源元件连接端子; IC芯片连接端子位于形成在最外层的树脂绝缘层中的开口中; 无源元件连接端子由形成在树脂绝缘层上的上端子部和位于树脂绝缘层中的上端子部的内侧的开口部的下端子部构成， 并且其中所述上端子部分的上表面高于参考表面，并且所述IC芯片连接端子和所述下端子部分的上表面的高度与所述基准表面的高度相同或更低。

    Multilayer Wiring Substrate, and Method of Manufacturing the Same
    6.
    发明申请
    Multilayer Wiring Substrate, and Method of Manufacturing the Same 失效
    多层接线基板及其制造方法

    公开(公告)号：US20110198114A1

    公开(公告)日：2011-08-18

    申请号：US13028545

    申请日：2011-02-16

    申请人： Shinnosuke MAEDA ,  Tetsuo SUZUKI ,  Satoshi HIRANO

    发明人： Shinnosuke MAEDA ,  Tetsuo SUZUKI ,  Satoshi HIRANO

    IPC分类号： H05K1/09 ,  H01R43/00 ,  H05K1/00

    CPC分类号： H05K3/4682 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K1/113 ,  H05K3/205 ,  H05K2201/09745 ,  H05K2201/099 ,  H05K2203/0361 ,  H05K2203/0369 ,  H05K2203/0588 ,  Y10T29/302 ,  Y10T29/49117 ,  H01L2924/00

    摘要： A plurality of openings are formed in a resin insulation layer on a top surface side of a wiring laminate portion, and a plurality of openings are formed in a resin insulation layer on a bottom surface side thereof. A plurality of connection terminals are disposed to correspond to the openings. Peripheral portions of terminal outer surfaces of the connection terminals are covered by the resin insulation layer on the top surface side, and peripheral portions of terminal outer surfaces of the connection terminals are covered by the resin insulation layer on the bottom surface side. Each of the second-main-surface-side connection terminals has a concave portion at the center of the terminal outer surface, and the deepest portion of the concave portion is located on the interior side in relation to the peripheral portion of the terminal outer surface.

    摘要翻译： 在布线层叠部的顶面侧的树脂绝缘层上形成有多个开口部，在其底面侧的树脂绝缘层上形成有多个开口部。 多个连接端子被设置成对应于这些开口。 连接端子的端子外表面的外围部分被顶表面侧上的树脂绝缘层覆盖，并且连接端子的端子外表面的周边部分被底表面侧上的树脂绝缘层覆盖。 每个第二主表面侧连接端子在端子外表面的中心具有凹部，并且凹部的最深部相对于端子外表面的周边部位于内侧 。

    METHOD OF MANUFACTURING GLASS SUBSTRATE
    8.
    发明申请
    METHOD OF MANUFACTURING GLASS SUBSTRATE 有权
    制造玻璃基板的方法

    公开(公告)号：US20090038743A1

    公开(公告)日：2009-02-12

    申请号：US12249341

    申请日：2008-10-10

    申请人： Tetsuo SUZUKI ,  Yoshio Kawakami

    发明人： Tetsuo SUZUKI ,  Yoshio Kawakami

    IPC分类号： B32B38/10

    CPC分类号： G11B5/8404 ,  B24B9/065

    摘要： A glass block is formed by stacking, fixing, and integrating a plurality of thin glass plates having a predetermined thickness. An annular glass block is formed by coring the glass block. Surfaces of an inside circumference and an outside circumference of the annular glass block are ground. The annular glass block of which the surfaces of the inside circumference and the outside circumference are ground are separated into individual annular glass substrates, and separated annular glass substrates are cleaned. Then, edge portions of the inside circumference and the outside circumference of a cleaned annular glass substrate are chamfered.

    摘要翻译： 通过堆叠，固定和整合具有预定厚度的多个薄玻璃板来形成玻璃块。 通过取芯玻璃块形成环形玻璃块。 研磨环形玻璃块的内周和外周的表面。 将内周面和外周面的表面研磨的环状玻璃块分离成单独的环状玻璃基板，并且分离的环状玻璃基板被清洁。 然后，将清洁后的环状玻璃基板的内周缘部和外周缘部进行倒角。

    DEVELOPER SUPPLY DEVICE AND IMAGE FORMING APPARATUS INCORPORATING SAME
    9.
    发明申请
    DEVELOPER SUPPLY DEVICE AND IMAGE FORMING APPARATUS INCORPORATING SAME 有权

    公开(公告)号：US20210018861A1

    公开(公告)日：2021-01-21

    申请号：US16887995

    申请日：2020-05-29

    申请人： Masashi OHNISHI ,  Tetsuo SUZUKI ,  Shingo KUBOKI

    发明人： Masashi OHNISHI ,  Tetsuo SUZUKI ,  Shingo KUBOKI

    IPC分类号： G03G15/08

    摘要： A developer supply device includes a body, a developer supply unit drawably insertable into the body, and a developer container removably installable in the developer supply unit. The developer container contains a developer and includes a developer discharge port. The developer supply unit includes a lever that closes the developer discharge port when the lever has moved to a first position and opens the developer discharge port when the lever has moved to a second position, and a lock that engages an engagement portion of the lever in conjunction with an operation of drawing the developer supply unit from the body to restrict the lever from moving from the first position to the second position and disengage from the engagement portion in conjunction with an operation of inserting the developer supply unit into the body to allow the lever to move from the first position to the second position.