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    Multilayered Wiring Substrate
    1.
    发明申请
    Multilayered Wiring Substrate 失效
    多层接线基板

    公开(公告)号：US20110156272A1

    公开(公告)日：2011-06-30

    申请号：US12976427

    申请日：2010-12-22

    申请人： Shinnosuke MAEDA ,  Tetsuo SUZUKI ,  Atsuhiko SUGIMOTO ,  Tatsuya ITO ,  Takuya HANDO ,  Satoshi HIRANO

    发明人： Shinnosuke MAEDA ,  Tetsuo SUZUKI ,  Atsuhiko SUGIMOTO ,  Tatsuya ITO ,  Takuya HANDO ,  Satoshi HIRANO

    IPC分类号： H01L23/48

    CPC分类号： H05K3/3452 ,  H01L23/49811 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K1/113 ,  H05K3/205 ,  H05K3/383 ,  H05K3/4682 ,  H05K2201/068 ,  H05K2201/094 ,  H05K2201/09527 ,  H05K2201/099 ,  H05K2203/0346 ,  H05K2203/0369 ,  H01L2924/00

    摘要： A multilayered wiring substrate, comprising: a plurality of first main surface side connecting terminals arranged in a first main surface of a stack structure; and a plurality of second main surface side connecting terminals being arranged in a second main surface of the stack structure; wherein a plurality of conductor layers are alternately formed in a plurality of stacked resin insulation layers and are operably connected to each other through via conductors tapered such that diameters thereof are widened toward the first or the second main surface, wherein a plurality of openings are formed in an exposed outermost resin insulation layer in the second main surface, and terminal outer surfaces of the second main surface side connecting terminals arranged to match with the plurality of the openings are positioned inwardly from an outer main surface of the exposed outermost resin insulation layer, and edges of terminal inner surfaces are rounded.

    摘要翻译： 一种多层布线基板，包括：布置在堆叠结构的第一主表面中的多个第一主表面侧连接端子; 并且多个第二主表面侧连接端子布置在所述堆叠结构的第二主表面中; 其中多个导体层交替地形成在多个堆叠的树脂绝缘层中，并且通过锥形的通孔导体可操作地连接，使得其直径朝向第一或第二主表面加宽，其中形成多个开口 在第二主表面中暴露的最外层树脂绝缘层中，并且布置成与多个开口相匹配的第二主表面侧连接端子的端子外表面从暴露的最外层树脂绝缘层的外主表面位于内侧， 并且端子内表面的边缘是圆形的。

    Multilayer Wiring Substrate
    2.
    发明申请
    Multilayer Wiring Substrate 审中-公开
    多层接线基板

    公开(公告)号：US20110155438A1

    公开(公告)日：2011-06-30

    申请号：US12978750

    申请日：2010-12-27

    申请人： Tatsuya ITO ,  Tetsuo SUZUKI ,  Takuya HANDO ,  Shinnosuke MAEDA ,  Atsuhiko SUGIMOTO ,  Satoshi HIRANO

    发明人： Tatsuya ITO ,  Tetsuo SUZUKI ,  Takuya HANDO ,  Shinnosuke MAEDA ,  Atsuhiko SUGIMOTO ,  Satoshi HIRANO

    IPC分类号： H05K1/11

    CPC分类号： H05K3/4682 ,  H05K1/113 ,  H05K3/4007 ,  H05K2201/094 ,  H05K2201/09427 ,  H05K2201/09472

    摘要： A multilayer wiring substrate has a multilayer wiring laminate portion in which a plurality of resin insulation layers made primarily of the same resin insulation material, and a plurality of conductive layers are laminated alternately. A plurality of first-main-surface-side connection terminals are disposed on one side of the laminate structure where a first main surface thereof is present, and a plurality of second-main-surface-side connection terminals being disposed on an other side of the laminate structure where a second main surface thereof is present. The plurality of conductive layers are formed in the plurality of resin insulation layers and interconnected by means of via conductors whose diameters increase toward the first main surface or the second main surface. The plurality of first-main-surface-side connection terminals comprising at least two types of terminals for connection of different articles-to-be-connected. Top surfaces of the plurality of first-main-surface-side connection terminals differ in height according to types of the articles-to-be-connected.

    摘要翻译： 多层布线基板具有多层布线层叠部，其中主要由相同树脂绝缘材料制成的多个树脂绝缘层和多个导电层交替层叠。 多个第一主表面侧连接端子设置在层叠结构的存在第一主表面的一侧上，并且多个第二主表面侧连接端子设置在 其中存在第二主表面的层压结构。 多个导电层形成在多个树脂绝缘层中，并且通过直径朝向第一主表面或第二主表面增大的通孔导体互连。 多个第一主表面侧连接端子包括用于连接不同待连接物品的至少两种类型的端子。 多个第一主表面侧连接端子的顶表面根据要连接的物品的类型而不同。

    MULTILAYER WIRING SUBSTRATE
    4.
    发明申请
    MULTILAYER WIRING SUBSTRATE 有权
    多层布线基板

    公开(公告)号：US20110232951A1

    公开(公告)日：2011-09-29

    申请号：US13070094

    申请日：2011-03-23

    申请人： Shinnosuke MAEDA ,  Tatsuya ITO ,  Satoshi HIRANO

    发明人： Shinnosuke MAEDA ,  Tatsuya ITO ,  Satoshi HIRANO

    IPC分类号： H05K1/09

    CPC分类号： H05K3/244 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49866 ,  H01L2924/0002 ,  H05K1/113 ,  H05K3/205 ,  H05K3/4682 ,  H05K2201/099 ,  H05K2203/0361 ,  H01L2924/00

    摘要： In a wiring laminate portion of a multilayer wiring substrate, a solder resist layer having a plurality of openings is disposed on a main surface side of the laminate structure, and connection terminals are embedded in an outermost resin insulation layer in contact with the solder resist layer. Each of the connection terminals comprises a copper layer and a metallic layer formed of at least one type of metal other than copper. A main-surface-side circumferential portion of the copper layer is covered by the solder resist layer. At least a portion of the metallic layer is located in a recess in a main-surface-side central portion of the copper layer. At least a portion of the metallic layer is exposed via a corresponding opening.

    摘要翻译： 在多层布线基板的布线层叠部分中，具有多个开口的阻焊层设置在层叠结构的主表面侧，并且连接端子嵌入在与阻焊层接触的最外层树脂绝缘层中 。 每个连接端子包括铜层和由铜以外的至少一种类型的金属形成的金属层。 铜层的主表面侧圆周部分被阻焊层覆盖。 金属层的至少一部分位于铜层的主表面侧中央部的凹部中。 金属层的至少一部分经由相应的开口露出。

    Method of Manufacturing Multilayer Wiring Substrate, and Multilayer Wiring Substrate
    5.
    发明申请
    Method of Manufacturing Multilayer Wiring Substrate, and Multilayer Wiring Substrate 有权
    制造多层接线基板和多层接线基板的方法

    公开(公告)号：US20110200788A1

    公开(公告)日：2011-08-18

    申请号：US13028588

    申请日：2011-02-16

    申请人： Shinnosuke MAEDA ,  Tetsuo SUZUKI ,  Satoshi HIRANO

    发明人： Shinnosuke MAEDA ,  Tetsuo SUZUKI ,  Satoshi HIRANO

    IPC分类号： B32B3/24 ,  H05K3/06

    CPC分类号： H05K3/4682 ,  H05K1/112 ,  H05K3/205 ,  H05K2201/094 ,  H05K2201/09472 ,  H05K2201/099 ,  Y10T428/24331 ,  Y10T428/24339

    摘要： A plurality of openings are formed in a resin insulation layer on a bottom surface side of a wiring laminate portion which constitutes a multilayer wiring substrate. A plurality of motherboard connection terminals are disposed to correspond to the openings. The motherboard connection terminals are primarily comprised of a copper layer, and peripheral portions of terminal outer surfaces thereof are covered by the outermost resin insulation layer. A dissimilar metal layer made of at least one metal which is lower in etching rate than copper is formed between an inner main surface of the outermost resin insulation layer and peripheral portions of the terminal outer surfaces.

    摘要翻译： 在构成多层布线基板的布线层叠体的底面侧的树脂绝缘层上形成有多个开口部。 多个主板连接端子被设置成对应于这些开口。 母板连接端子主要由铜层构成，其端子外表面的周边部分被最外层树脂绝缘层覆盖。 在最外层树脂绝缘层的内主表面和端子外表面的周边部分之间形成由蚀刻速率低于铜的至少一种金属制成的异种金属层。

    Multilayer Wiring Substrate and Method of Manufacturing the Same
    6.
    发明申请
    Multilayer Wiring Substrate and Method of Manufacturing the Same 失效
    多层接线基板及其制造方法

    公开(公告)号：US20110211320A1

    公开(公告)日：2011-09-01

    申请号：US13031735

    申请日：2011-02-22

    申请人： Shinnosuke MAEDA ,  Takuya TORII ,  Tetsuo SUZUKI ,  Satoshi HIRANO

    发明人： Shinnosuke MAEDA ,  Takuya TORII ,  Tetsuo SUZUKI ,  Satoshi HIRANO

    IPC分类号： H05K7/00 ,  H05K3/36

    CPC分类号： H01L21/6835 ,  H01L23/3107 ,  H01L23/49811 ,  H01L23/49822 ,  H01L2221/68345 ,  H01L2924/0002 ,  H01L2924/19041 ,  H05K3/244 ,  H05K3/4682 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

    摘要： A multilayer wiring substrate includes first principal surface side connection terminals arranged on a first principal surface of a stacked configuration; wherein, the first principal surface side connection terminals include an IC chip connection terminal, and a passive element connection terminal; the IC chip connection terminal is located in an opening formed in a resin insulating layer of an uppermost outer layer; the passive element connection terminal is formed of an upper terminal part formed on the resin insulating layer, and a lower terminal part located in an opening formed at a portion of an inner side of the upper terminal part in the resin insulating layer; and, wherein an upper face of the upper terminal part is higher than a reference surface, and an upper face of the IC chip connection terminal and the lower terminal part are identical in height to or lower in height than the reference surface.

    摘要翻译： 多层布线基板包括布置在堆叠构造的第一主表面上的第一主表面侧连接端子; 其中，所述第一主面侧连接端子包括IC芯片连接端子和无源元件连接端子; IC芯片连接端子位于形成在最外层的树脂绝缘层中的开口中; 无源元件连接端子由形成在树脂绝缘层上的上端子部和位于树脂绝缘层中的上端子部的内侧的开口部的下端子部构成， 并且其中所述上端子部分的上表面高于参考表面，并且所述IC芯片连接端子和所述下端子部分的上表面的高度与所述基准表面的高度相同或更低。

    Multilayer Wiring Substrate, and Method of Manufacturing the Same
    7.
    发明申请
    Multilayer Wiring Substrate, and Method of Manufacturing the Same 失效
    多层接线基板及其制造方法

    公开(公告)号：US20110198114A1

    公开(公告)日：2011-08-18

    申请号：US13028545

    申请日：2011-02-16

    申请人： Shinnosuke MAEDA ,  Tetsuo SUZUKI ,  Satoshi HIRANO

    发明人： Shinnosuke MAEDA ,  Tetsuo SUZUKI ,  Satoshi HIRANO

    IPC分类号： H05K1/09 ,  H01R43/00 ,  H05K1/00

    CPC分类号： H05K3/4682 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K1/113 ,  H05K3/205 ,  H05K2201/09745 ,  H05K2201/099 ,  H05K2203/0361 ,  H05K2203/0369 ,  H05K2203/0588 ,  Y10T29/302 ,  Y10T29/49117 ,  H01L2924/00

    摘要： A plurality of openings are formed in a resin insulation layer on a top surface side of a wiring laminate portion, and a plurality of openings are formed in a resin insulation layer on a bottom surface side thereof. A plurality of connection terminals are disposed to correspond to the openings. Peripheral portions of terminal outer surfaces of the connection terminals are covered by the resin insulation layer on the top surface side, and peripheral portions of terminal outer surfaces of the connection terminals are covered by the resin insulation layer on the bottom surface side. Each of the second-main-surface-side connection terminals has a concave portion at the center of the terminal outer surface, and the deepest portion of the concave portion is located on the interior side in relation to the peripheral portion of the terminal outer surface.

    摘要翻译： 在布线层叠部的顶面侧的树脂绝缘层上形成有多个开口部，在其底面侧的树脂绝缘层上形成有多个开口部。 多个连接端子被设置成对应于这些开口。 连接端子的端子外表面的外围部分被顶表面侧上的树脂绝缘层覆盖，并且连接端子的端子外表面的周边部分被底表面侧上的树脂绝缘层覆盖。 每个第二主表面侧连接端子在端子外表面的中心具有凹部，并且凹部的最深部相对于端子外表面的周边部位于内侧 。

    Multilayered Wiring Board and Method of Manufacturing the Same
    8.
    发明申请
    Multilayered Wiring Board and Method of Manufacturing the Same 失效
    多层接线板及其制造方法

    公开(公告)号：US20110209910A1

    公开(公告)日：2011-09-01

    申请号：US13034792

    申请日：2011-02-25

    申请人： Shinnosuke MAEDA ,  Satoshi HIRANO

    发明人： Shinnosuke MAEDA ,  Satoshi HIRANO

    IPC分类号： H05K1/11 ,  H01R9/00

    CPC分类号： H05K3/4682 ,  H05K1/112 ,  H05K3/205 ,  H05K2201/094 ,  H05K2201/09472 ,  H05K2201/099 ,  Y10T29/49147

    摘要： A multilayered wiring board having a stack structure multilayered by alternately stacking a plurality of conductor layers and a plurality of resin insulation layers, wherein a solder resist is provided on at least one of a first main surface side and a second main surface side of the stack structure, a plurality of openings are formed in an outermost resin insulation layer that contacts with the solder resist, a plurality of the first main surface side connecting terminals or a plurality of the second main surface side connecting terminals being made of a copper layer as a main component and positioned in a plurality of the openings, terminal outer surfaces being positioned inwardly from an outer surface of the outermost resin insulation layer, and the solder resist extends into the plurality of openings and makes contact with an outer circumference portion of each of the terminal outer surfaces.

    摘要翻译： 一种多层布线基板，其具有通过交替堆叠多个导体层和多个树脂绝缘层而叠层的叠层结构，其中在所述堆叠的第一主表面侧和第二主表面侧中的至少一个上设置阻焊剂 结构中，在与阻焊剂接触的最外层树脂绝缘层中形成多个开口，多个第一主表面侧连接端子或多个第二主表面侧连接端子由铜层制成， 主要部件并且定位在多个开口中，端子外表面从最外层树脂绝缘层的外表面向内定位，并且阻焊剂延伸到多个开口中并与每个的外周部分接触 端子外表面。

    MULTILAYER WIRING BOARD AND MANUFACTURING METHOD THEREOF
    10.
    发明申请
    MULTILAYER WIRING BOARD AND MANUFACTURING METHOD THEREOF 失效
    多层接线板及其制造方法

    公开(公告)号：US20120018194A1

    公开(公告)日：2012-01-26

    申请号：US13184661

    申请日：2011-07-18

    申请人： Shinnosuke MAEDA ,  Satoshi HIRANO ,  Yuuki SHIIBA

    发明人： Shinnosuke MAEDA ,  Satoshi HIRANO ,  Yuuki SHIIBA

    IPC分类号： H05K1/02 ,  H05K3/10

    CPC分类号： H05K3/0035 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1461 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0373 ,  H05K3/4644 ,  H05K2201/0209 ,  H05K2201/09827 ,  Y10T29/49165 ,  H01L2924/00

    摘要： Disclosed is a manufacturing method of a multilayer wiring board. The multilayer wiring board includes an outer resin insulation layer made of an insulating resin material, containing a filler of inorganic filler and having an outer surface defining a chip mounting area to which an electronic chip is mounted with an underfill material filled in between the outer resin insulation layer and the electronic chip and holes through which conductor parts are exposed. The manufacturing method includes a hole forming step of forming the holes in the outer resin insulation layer by laser processing, a desmear treatment step of, after the hole forming step, removing smears from inside the holes of the outer resin insulation layer, and a filler reducing step of, after the desmear treatment step, reducing the amount of the filler exposed at the outer surface of the outer resin insulation layer.

    摘要翻译： 公开了一种多层布线板的制造方法。 多层布线基板包括由绝缘树脂材料制成的外部树脂绝缘层，其包含无机填料的填料并且具有限定芯片安装区域的外表面，电子芯片安装在该芯片安装区域，底部填充材料填充在外部树脂 绝缘层以及导体部件露出的电子芯片和孔。 该制造方法包括：通过激光加工在外树脂绝缘层中形成孔的孔形成步骤，在孔形成步骤之后的去污处理步骤，从外树脂绝缘层的孔内部除去污迹，以及填料 在去污处理步骤之后，减少在外树脂绝缘层的外表面暴露的填料的量。