公开(公告)号：US5805628A

公开(公告)日：1998-09-08

申请号：US735637

申请日：1996-10-23

申请人： Shoichi Karakida ,  Norio Hayafuji ,  Tatsuya Kimura ,  Motoharu Miyashita ,  Hirotaka Kizuki ,  Takashi Nishimura

发明人： Shoichi Karakida ,  Norio Hayafuji ,  Tatsuya Kimura ,  Motoharu Miyashita ,  Hirotaka Kizuki ,  Takashi Nishimura

IPC分类号： H01S5/00 ,  H01S5/10 ,  H01S5/16 ,  H01S5/20 ,  H01S5/223 ,  H01S5/343 ,  H01S3/19

CPC分类号： B82Y20/00 ,  H01S5/10 ,  H01S5/16 ,  H01S5/2231 ,  H01S5/1064 ,  H01S5/2077 ,  H01S5/3432

摘要： A semiconductor laser device includes a semiconductor substrate of a first conductivity type; opposed light emitting facets; a double heterojunction structure disposed on the semiconductor substrate and including an optical waveguide that extends between the facets and comprises a light emitting region and a lens region, the lens region being between the light emitting region and one of the facets, the double heterojunction structure including a plurality of AlGaAs series compound semiconductor layers which are thicker in the light emitting region than in the lens region; and a current blocking structure disposed on both sides of the double heterojunction structure and including a lower AlGaAs series compound semiconductor layer of the first conductivity type, an intermediate AlGaAs series compound semiconductor layer of a second conductivity type, opposite the first conductivity type, and an upper AlGaAs series compound semiconductor layer of the first conductivity type. Therefore, a reactive current that does not contribute to laser oscillation is prevented from flowing through the current blocking structure.

摘要翻译： 半导体激光器件包括第一导电类型的半导体衬底; 相对的发光面; 双异质结结构，其设置在所述半导体衬底上，并且包括在所述面之间延伸并且包括发光区域和透镜区域的光波导，所述透镜区域在所述发光区域和所述面之一之间，所述双异质结结构包括 多个AlGaAs系化合物半导体层，其在发光区域比透镜区域厚; 以及设置在双异质结结构的两侧上的电流阻挡结构，并且包括第一导电类型的下AlGaAs系化合物半导体层，与第一导电类型相反的第二导电类型的中间AlGaAs系化合物半导体层和 第一导电类型的上AlGaAs系化合物半导体层。 因此，防止无助于激光振荡的无功电流流过电流阻挡结构。

公开(公告)号：US06358316B1

公开(公告)日：2002-03-19

申请号：US08513036

申请日：1995-08-09

申请人： Hirotaka Kizuki ,  Norio Hayafuji ,  Tatsuya Kimura

发明人： Hirotaka Kizuki ,  Norio Hayafuji ,  Tatsuya Kimura

IPC分类号： C30B2504

CPC分类号： B82Y20/00 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/02395 ,  H01L21/02463 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/30621 ,  H01L21/3081 ,  H01L21/314 ,  H01L29/66469 ,  H01S5/2081 ,  H01S5/2231 ,  H01S5/227 ,  H01S5/2275 ,  H01S5/3203 ,  H01S5/32308 ,  H01S5/341 ,  H01S5/3432 ,  H01S5/4031 ,  H01S5/4043

摘要： In a method for producing a semiconductor device, a compound semiconductor cap layer including no aluminum is grown on a compound semiconductor layer including aluminum, a mask pattern insulating film is formed on a part of the compound semiconductor cap layer, the compound semiconductor wafer with the insulating mask pattern is immersed in an ammonium sulfide solution, the compound semiconductor wafer is selectively etched away using a chlorine containing gas in a reaction chamber, and a groove formed in the etching process is filled with a compound semiconductor layer grown in the reaction chamber by MOCVD. Therefore, a regrowth interface on which no impurity is segregated is attained, improving the quality of the regrown crystal layer.

摘要翻译： 在半导体装置的制造方法中，在包含铝的化合物半导体层上生长不含铝的化合物半导体盖层，在化合物半导体盖层的一部分上形成有掩模图案绝缘膜，具有 将绝缘掩模图案浸入硫化铵溶液中，在反应室中使用含氯气体选择性地蚀刻掉化合物半导体晶片，并且在蚀刻工艺中形成的凹槽中填充在反应室中生长的化合物半导体层， MOCVD。 因此，可以获得没有杂质分离的再生界面，提高再结晶层的质量。

公开(公告)号：US5426658A

公开(公告)日：1995-06-20

申请号：US200483

申请日：1994-02-23

申请人： Nobuaki Kaneno ,  Hirotaka Kizuki ,  Norio Hayafuji ,  Tetsuo Shiba ,  Hitoshi Tada

发明人： Nobuaki Kaneno ,  Hirotaka Kizuki ,  Norio Hayafuji ,  Tetsuo Shiba ,  Hitoshi Tada

IPC分类号： H01L21/20 ,  H01L21/308 ,  H01S5/20 ,  H01S5/223 ,  H01S5/227 ,  H01S5/323 ,  H01S3/19

CPC分类号： H01L21/3081 ,  H01L21/02392 ,  H01L21/02395 ,  H01L21/02463 ,  H01L21/02505 ,  H01L21/02546 ,  H01L21/0262 ,  H01S5/2231 ,  H01S2304/04 ,  H01S5/2081 ,  H01S5/2277 ,  H01S5/32325

摘要： A semiconductor laser device including a semiconductor substrate; a plurality of semiconductor layers including an AlGaAs layer epitaxially grown on said semiconductor substrate; a ridge having a reverse mesa shape and opposed sides formed of said plurality of semiconductor layers; an Al.sub.x Ga.sub.1-x As low temperature buffer layer (0.ltoreq..times..ltoreq.1) disposed on said AlGaAs layer at opposite sides of said ridge; a first semiconductor layer epitaxially disposed on said low temperature buffer layer at opposite sides of said ridge; and a second semiconductor layer epitaxially disposed on said ridge and said first semiconductor layer.

摘要翻译： 一种半导体激光器件，包括半导体衬底; 包括在所述半导体衬底上外延生长的AlGaAs层的多个半导体层; 具有反台面形状的脊和由所述多个半导体层形成的相对侧; 在所述脊的相对侧设置在所述AlGaAs层上的Al x Ga 1-x As低温缓冲层（0≤x≤1） 在所述脊的相对侧外延地设置在所述低温缓冲层上的第一半导体层; 以及外延地设置在所述脊和所述第一半导体层上的第二半导体层。

公开(公告)号：US5796127A

公开(公告)日：1998-08-18

申请号：US915791

申请日：1997-08-21

申请人： Norio Hayafuji ,  Yoshitsugu Yamamoto ,  Hirotaka Kizuki

发明人： Norio Hayafuji ,  Yoshitsugu Yamamoto ,  Hirotaka Kizuki

IPC分类号： H01L29/812 ,  H01L21/203 ,  H01L21/314 ,  H01L21/324 ,  H01L21/335 ,  H01L21/338 ,  H01L23/31 ,  H01L29/36 ,  H01L29/778 ,  H01L29/201 ,  H01L29/737

CPC分类号： H01L29/66462 ,  H01L21/314 ,  H01L21/3245 ,  H01L23/3185 ,  H01L29/365 ,  H01L2924/0002

摘要： A method of fabricating a semiconductor device includes forming a first mixed crystal semiconductor layer of AlAs and InAs; applying a solution containing a material easily combining with fluorine to the surface of the first mixed crystal semiconductor layer exposed to the atmosphere so that the material combines with fluorine that sticks to the surface of the first mixed crystal semiconductor layer; and annealing the first mixed crystal semiconductor layer in a vacuum. In this method, since the fluorine on the surface of the first mixed crystal semiconductor layer exposed to the atmosphere combines with the material included in the solution and is removed together with the material, a first mixed crystal semiconductor layer having no fluorine is produced. Therefore, unwanted infiltration of fluorine into the first mixed crystal semiconductor layer is avoided, resulting in a highly reliable semiconductor device with desired characteristics.

摘要翻译： 制造半导体器件的方法包括：形成AlAs和InAs的第一混晶半导体层; 将含有容易与氟结合的材料的溶液施加到暴露于大气的第一混晶半导体层的表面，使得该材料与粘附在第一混晶半导体层表面的氟结合; 以及在真空中退火所述第一混晶半导体层。 在该方法中，由于暴露于大气中的第一混晶半导体层的表面上的氟与包含在溶液中的材料结合，与材料一起被除去，因此产生不含氟的第一混晶半导体层。 因此，避免了氟进入第一混晶半导体层的不必要的渗入，导致具有所需特性的高度可靠的半导体器件。

公开(公告)号：US5602414A

公开(公告)日：1997-02-11

申请号：US260791

申请日：1994-06-16

申请人： Kotaro Mitsui ,  Zenpei Kawazu ,  Kazuo Mizuguchi ,  Seiji Ochi ,  Yuji Ohkura ,  Norio Hayafuji ,  Hirotaka Kizuki ,  Mari Tsugami ,  Akihiro Takami ,  Manabu Katoh

发明人： Kotaro Mitsui ,  Zenpei Kawazu ,  Kazuo Mizuguchi ,  Seiji Ochi ,  Yuji Ohkura ,  Norio Hayafuji ,  Hirotaka Kizuki ,  Mari Tsugami ,  Akihiro Takami ,  Manabu Katoh

IPC分类号： H01L27/14 ,  H01L27/146 ,  H01L31/10 ,  H01L31/00

CPC分类号： H01L27/14649

摘要： In a method for fabricating an infrared detector, initially, a CdHgTe layer of a first conductivity type is produced on a front surface of a semiconductor substrate, a plurality of spaced apart CdHgTe regions of a second conductivity type, opposite the first conductivity type, are produced at the surface of the first conductivity type CdHgTe layer, and part of the surface of the first conductivity type CdHgTe layer between the second conductivity type CdHgTe regions is selectively irradiated with a charged particle beam to evaporate Hg atoms from that part, whereby a CdHgTe separation region of the first conductivity type and having a Cd composition larger than that of the first conductivity type CdHgTe layer is produced penetrating through the first conductivity type CdHgTe layer and surrounding each of the second conductivity type CdHgTe regions. Therefore, a highly-integrated high-resolution infrared detector with no crosstalk between pixels is achieved.

摘要翻译： 在红外线检测器的制造方法中，首先，在半导体基板的正面形成有与第一导电型相反的多个第二导电类型的间隔开的CdHgTe区域的第一导电型CdHgTe层， 在第一导电型CdHgTe层的表面产生，并且第二导电型CdHgTe区域之间的第一导电类型CdHgTe层的表面的一部分被带电粒子束选择性地照射，以从该部分蒸发Hg原子，由此CdHgTe 产生具有比第一导电型CdHgTe层的Cd组分大的第一导电类型的分离区，穿过第一导电型CdHgTe层并围绕每个第二导电型CdHgTe区。 因此，实现了在像素之间没有串扰的高度集成的高分辨率红外检测器。

公开(公告)号：US5316967A

公开(公告)日：1994-05-31

申请号：US975109

申请日：1992-11-12

申请人： Nobuaki Kaneno ,  Hirotaka Kizuki ,  Norio Hayafuji ,  Tetsuo Shiba ,  Hitoshi Tada

发明人： Nobuaki Kaneno ,  Hirotaka Kizuki ,  Norio Hayafuji ,  Tetsuo Shiba ,  Hitoshi Tada

IPC分类号： H01L21/20 ,  H01L21/308 ,  H01S5/20 ,  H01S5/223 ,  H01S5/227 ,  H01S5/323

CPC分类号： H01L21/3081 ,  H01L21/02392 ,  H01L21/02395 ,  H01L21/02463 ,  H01L21/02505 ,  H01L21/02546 ,  H01L21/0262 ,  H01S5/2231 ,  H01S2304/04 ,  H01S5/2081 ,  H01S5/2277 ,  H01S5/32325

摘要： In a method for producing a semiconductor device, a first semiconductor layer is epitaxially grown on a semiconductor substrate, an insulating film pattern is formed on the first semiconductor layer, and portions of the first semiconductor layer are removed by wet etching using the insulating film pattern as a mask to leave a ridge having a reverse mesa shape and a width. Ends of the insulating film pattern are removed by etching to approximately the width of the ridge, a second semiconductor layer is epitaxially grown on opposite sides of the ridge, and a third semiconductor layer is epitaxially grown on the ridge and the second semiconductor layer. The second semiconductor layer is evenly grown without concave portions at opposite sides of the ridge. In addition, the third semiconductor layer is evenly grown on the ridge and the second semiconductor layer, and an electrode reliably connects the surface of the third semiconductor layer. A semiconductor device with good performance and high reliability is reproducibly manufactured.

摘要翻译： 在制造半导体器件的方法中，在半导体衬底上外延生长第一半导体层，在第一半导体层上形成绝缘膜图案，并且通过使用绝缘膜图案的湿蚀刻去除第一半导体层的部分 作为掩模，离开具有反台面形状和宽度的脊。 绝缘膜图案的端部通过蚀刻到脊的宽度去除，在脊的相对侧上外延生长第二半导体层，并且在脊和第二半导体层上外延生长第三半导体层。 第二半导体层在脊的相对侧均匀生长而没有凹部。 此外，第三半导体层均匀地生长在脊和第二半导体层上，并且电极可靠地连接第三半导体层的表面。 可重复地制造具有良好性能和高可靠性的半导体器件。

公开(公告)号：US5439723A

公开(公告)日：1995-08-08

申请号：US150879

申请日：1993-11-12

申请人： Motoharu Miyashita ,  Norio Hayafuji ,  Yutaka Mihashi

发明人： Motoharu Miyashita ,  Norio Hayafuji ,  Yutaka Mihashi

IPC分类号： H01L21/02 ,  B28D5/00 ,  C30B33/00 ,  H01L21/68 ,  B32B3/02

CPC分类号： B28D5/0005 ,  B28D5/0011 ,  C30B33/00 ,  Y10T428/219 ,  Y10T428/24273 ,  Y10T428/24298 ,  Y10T428/24306 ,  Y10T428/24314 ,  Y10T428/24479 ,  Y10T428/2457 ,  Y10T428/24777

摘要： A semiconductor wafer includes a notch or a hole used in preparing an orientation flat on the wafer. The notch in the wafer includes a side that is perpendicular to the surfaces of the wafer and aligned along a cleavage plane of the wafer for forming the orientation flat by cleaving. A hole in a wafer preferably includes an axis aligned along the cleaving plane. A sharp, non-rounded cleavage is formed by preparing the notch or hole after the completion of any etching processes or other steps that may round the edges of the flat. The sharp edges aid in achieving a precision alignment using the orientation flat.

摘要翻译： 半导体晶片包括用于制备晶片上的定向平面的凹口或孔。 晶片中的凹口包括垂直于晶片表面并沿着晶片的解理平面排列的一侧，用于通过切割形成取向平面。 晶片中的孔优选地包括沿着切割平面对准的轴。 通过在完成任何蚀刻工艺之后制备凹口或孔而形成尖锐的非圆形裂纹，或者可以在平面边缘周围的其它步骤。 锋利的边缘有助于使用定向平板实现精确对准。

公开(公告)号：US5279077A

公开(公告)日：1994-01-18

申请号：US977154

申请日：1992-11-16

申请人： Motoharu Miyashita ,  Norio Hayafuji ,  Yutaka Mihashi

发明人： Motoharu Miyashita ,  Norio Hayafuji ,  Yutaka Mihashi

IPC分类号： H01L21/02 ,  B28D5/00 ,  C30B33/00 ,  H01L21/68 ,  B24B49/00

CPC分类号： B28D5/0005 ,  B28D5/0011 ,  C30B33/00 ,  Y10T428/219 ,  Y10T428/24273 ,  Y10T428/24298 ,  Y10T428/24306 ,  Y10T428/24314 ,  Y10T428/24479 ,  Y10T428/2457 ,  Y10T428/24777

摘要： In a method for forming a semiconductor wafer with an orientation flat along a cleavage plane, a groove or hole is formed in the substrate on a line along which the substrate is cleaved to form an orientation flat and the substrate is treated to produce a mirrorlike surface. Then, the substrate having the mirrorlike surface is cleaved from the groove or hole to form the orientation flat. Accordingly, edges of the cleavage plane are not rounded due to the surface treatment. In addition, the substrate is easily cleaved along the cleavage plane from the groove or the hole. As a result, a semiconductor wafer having a sharp cleavage plane as an orientation flat is produced with improved yield, and alignment is performed with high precision in a subsequent process, such as photolithography.

摘要翻译： 在沿着解理面形成具有取向平坦的半导体晶片的方法中，在基板上的基板上形成凹槽或孔，沿着基板被切割以形成取向平面，并且将基板处理以产生反射镜表面 。 然后，具有镜面表面的基板从凹槽或孔中分离以形成取向平面。 因此，由于表面处理，解理面的边缘不会变圆。 此外，衬底沿着解理平面容易地从凹槽或孔中裂开。 结果，以提高的产量制造具有作为取向平面的尖锐解理面的半导体晶片，并且在随后的工艺（例如光刻）中以高精度进行对准。

公开(公告)号：US5315133A

公开(公告)日：1994-05-24

申请号：US928746

申请日：1992-08-13

申请人： Norio Hayafuji

发明人： Norio Hayafuji

IPC分类号： H01L21/205 ,  H01L21/331 ,  H01L29/205 ,  H01L29/73 ,  H01L29/737 ,  H01S5/00 ,  H01L33/00

CPC分类号： H01L21/0262 ,  H01L21/02546 ,  H01L21/02576 ,  H01L21/02579 ,  Y10S438/925

摘要： While depositing a III-V compound semiconductor layer from a vapor, carbon is added to group III and V elements to produce a p type conductivity region in the depositing semiconductor layer. Then, a small amount of n type dopant is added to the group III and V elements together with the carbon to produce an n type conductivity region in the depositing semiconductor layer. A sharp and precisely controlled doping profile is produced in the vicinity of a p-n junction, resulting in a semiconductor device having good initial performance and high reliability.

摘要翻译： 在从蒸气中沉积III-V化合物半导体层的同时，将碳添加到III族和V族元素中，以在沉积半导体层中产生p型导电性区域。 然后，少量的n型掺杂剂与碳一起添加到III族和V族元素中，以在沉积半导体层中产生n型导电性区域。 在p-n结附近产生尖锐和精确控制的掺杂分布，导致半导体器件具有良好的初始性能和高可靠性。

公开(公告)号：US5728215A

公开(公告)日：1998-03-17

申请号：US555707

申请日：1995-11-14

申请人： Takushi Itagaki ,  Masayoshi Takemi ,  Norio Hayafuji

发明人： Takushi Itagaki ,  Masayoshi Takemi ,  Norio Hayafuji

IPC分类号： H01L21/205 ,  C23C16/04 ,  H01S5/00 ,  C30B25/04

CPC分类号： C23C16/042

摘要： A method for forming a film by selective area growth by MDCVD technique includes forming a mask on a semiconductor substrate having a (100) plane, the mask having a mask opening to selectively growing a compound semiconductor layer, and a slit which is narrower than the mask opening in width and controls the growth rate of the compound semiconductor layer at the mask opening; and selectively growing the compound semiconductor layer at a growth rate which is on the mask in the mask opening and the slit.

摘要翻译： 通过MDCVD技术通过选择性区域生长形成膜的方法包括在具有（100）面的半导体衬底上形成掩模，掩模具有掩模开口以选择性地生长化合物半导体层，以及狭缝比 掩模开口宽度并控制化合物半导体层在掩模开口处的生长速率; 并且以掩模开口和狭缝中的掩模上的生长速率选择性地生长化合物半导体层。