公开(公告)号：US20100317161A1

公开(公告)日：2010-12-16

申请号：US12862197

申请日：2010-08-24

申请人： Shunpei YAMAZAKI ,  Akiharu MIYANAGA ,  Ko INADA ,  Yuji IWAKI

发明人： Shunpei YAMAZAKI ,  Akiharu MIYANAGA ,  Ko INADA ,  Yuji IWAKI

IPC分类号： H01L21/336 ,  H01L21/762

CPC分类号： H01L21/76254 ,  H01L21/2236 ,  H01L21/26506

摘要： To provide a method for manufacturing an SOI substrate having a single crystal semiconductor layer having a small and uniform thickness over an insulating film. Further, time of adding hydrogen ions is reduced and time of manufacture per SOI substrate is reduced. A bond layer is formed over a surface of a first semiconductor wafer and a separation layer is formed below the bond layer by irradiating the first semiconductor wafer with H3+ ions by an ion doping apparatus. H3+ ions accelerated by high voltage are separated to be three H+ ions at a semiconductor wafer surface, and the H+ ions cannot enter deeply. Therefore, H+ ions are added into a shallower region in the semiconductor wafer at a higher concentration than the case of using a conventional ion implantation method.

摘要翻译： 提供一种制造具有在绝缘膜上具有小而均匀厚度的单晶半导体层的SOI衬底的方法。 此外，加入氢离子的时间减少，并且每个SOI衬底的制造时间减少。 在第一半导体晶片的表面上形成接合层，并且通过用离子掺杂装置用H3 +离子照射第一半导体晶片，在接合层的下方形成分离层。 通过高压加速的H3 +离子在半导体晶片表面被分离为三个H +离子，并且H +离子不能深入。 因此，与使用常规的离子注入方法的情况相比，将H +离子加入到半导体晶片的较浅的区域中。

公开(公告)号：US20120061663A1

公开(公告)日：2012-03-15

申请号：US13226713

申请日：2011-09-07

申请人： Shunpei YAMAZAKI ,  Yusuke NONAKA ,  Takayuki INOUE ,  Masashi TSUBUKU ,  Kengo AKIMOTO ,  Akiharu MIYANAGA

发明人： Shunpei YAMAZAKI ,  Yusuke NONAKA ,  Takayuki INOUE ,  Masashi TSUBUKU ,  Kengo AKIMOTO ,  Akiharu MIYANAGA

IPC分类号： H01L29/12 ,  H01L21/34

CPC分类号： H01L29/7869 ,  H01L21/02488 ,  H01L21/02554 ,  H01L21/02565 ,  H01L29/04 ,  H01L29/24 ,  H01L29/78603

摘要： An object is to provide a semiconductor device including an oxide semiconductor film, which has stable electrical characteristics and high reliability. A stack of first and second material films is formed by forming the first material film (a film having a hexagonal crystal structure) having a thickness of 1 nm to 10 nm over an insulating surface and forming the second material film having a hexagonal crystal structure (a crystalline oxide semiconductor film) using the first material film as a nucleus. As the first material film, a material film having a wurtzite crystal structure (e.g., gallium nitride or aluminum nitride) or a material film having a corundum crystal structure (α-Al2O3, α-Ga2O3, In2O3, Ti2O3, V2O3, Cr2O3, or α-Fe2O3) is used.

摘要翻译： 本发明的目的是提供一种具有稳定的电气特性和高可靠性的氧化物半导体膜的半导体装置。 通过在绝缘表面上形成厚度为1nm至10nm的第一材料膜（具有六方晶体结构的膜）形成第一和第二材料膜的叠层，并形成具有六方晶系结构的第二材料膜（ 使用第一材料膜作为核的结晶氧化物半导体膜）。 作为第一材料膜，具有纤锌矿晶体结构的材料膜（例如氮化镓或氮化铝）或具有刚玉晶体结构的材料膜（α-Al 2 O 3，α-Ga 2 O 3，In 2 O 3，Ti 2 O 3，V 2 O 3，Cr 2 O 3，或 α-Fe 2 O 3）。

公开(公告)号：US20110318875A1

公开(公告)日：2011-12-29

申请号：US13230905

申请日：2011-09-13

申请人： Shunpei YAMAZAKI ,  Hidekazu MIYAIRI ,  Akiharu MIYANAGA ,  Kengo AKIMOTO ,  Kojiro SHIRAISHI

发明人： Shunpei YAMAZAKI ,  Hidekazu MIYAIRI ,  Akiharu MIYANAGA ,  Kengo AKIMOTO ,  Kojiro SHIRAISHI

IPC分类号： H01L21/34

CPC分类号： H01L29/66772 ,  H01L29/6675 ,  H01L29/78618 ,  H01L29/7869

摘要： An embodiment is to include a staggered (top gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.

摘要翻译： 一个实施例是包括交错（顶栅结构）薄膜晶体管，其中使用含有In，Ga和Zn的氧化物半导体膜作为半导体层，并且缓冲层设置在半导体层与源极和漏极之间 层。 有意地在源极和漏极电极层与半导体层之间提供具有比半导体层高的载流子浓度的缓冲层，从而形成欧姆接触。

公开(公告)号：US20110062436A1

公开(公告)日：2011-03-17

申请号：US12880343

申请日：2010-09-13

申请人： Shunpei YAMAZAKI ,  Masayuki SAKAKURA ,  Ryosuke WATANABE ,  Junichiro SAKATA ,  Kengo AKIMOTO ,  Akiharu MIYANAGA ,  Takuya HIROHASHI ,  Hideyuki KISHIDA

发明人： Shunpei YAMAZAKI ,  Masayuki SAKAKURA ,  Ryosuke WATANABE ,  Junichiro SAKATA ,  Kengo AKIMOTO ,  Akiharu MIYANAGA ,  Takuya HIROHASHI ,  Hideyuki KISHIDA

IPC分类号： H01L29/12

CPC分类号： H01L29/7869 ,  H01L27/1225 ,  H01L29/04 ,  H01L29/045 ,  H01L29/78618 ,  H01L29/78693 ,  H01L29/78696

摘要： To provide a transistor having a favorable electric characteristics and high reliability and a display device including the transistor. The transistor is a bottom-gate transistor formed using an oxide semiconductor for a channel region. An oxide semiconductor layer subjected to dehydration or dehydrogenation through heat treatment is used as an active layer. The active layer includes a first region of a superficial portion microcrystallized and a second region of the rest portion. By using the oxide semiconductor layer having such a structure, a change to an n-type, which is attributed to entry of moisture to the superficial portion or elimination of oxygen from the superficial portion, and generation of a parasitic channel can be suppressed. In addition, contact resistance between the oxide semiconductor layer and source and drain electrodes can be reduced.

摘要翻译： 提供具有良好的电特性和高可靠性的晶体管以及包括该晶体管的显示装置。 晶体管是使用用于沟道区的氧化物半导体形成的底栅晶体管。 使用通过热处理进行脱水或脱氢的氧化物半导体层作为活性层。 有源层包括微结晶的浅表部分的第一区域和其余部分的第二区域。 通过使用具有这种结构的氧化物半导体层，可以抑制归因于表层部分的水分进入或从表面部分的氧的消除导致的n型变化，以及寄生通道的产生。 此外，可以减小氧化物半导体层与源极和漏极之间的接触电阻。

公开(公告)号：US20100255645A1

公开(公告)日：2010-10-07

申请号：US12750739

申请日：2010-03-31

申请人： Shunpei YAMAZAKI ,  Akiharu MIYANAGA ,  Masahiro TAKAHASHI ,  Takuya HIROHASHI

发明人： Shunpei YAMAZAKI ,  Akiharu MIYANAGA ,  Masahiro TAKAHASHI ,  Takuya HIROHASHI

IPC分类号： H01L21/86

CPC分类号： H01L27/1251 ,  H01L21/0237 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02675 ,  H01L21/02686 ,  H01L27/1281

摘要： An island-shaped single crystal semiconductor layer whose top surface has a plane within ±10° from a {211} plane is formed on an insulating surface; a non-single-crystal semiconductor layer is formed in contact with the top surface and a side surface of the single crystal semiconductor layer and on the insulating surface; the non-single-crystal semiconductor layer is irradiated with laser light to melt the non-single-crystal semiconductor layer, and to crystallize the non-single-crystal semiconductor layer formed on the insulating surface with use of the single crystal semiconductor layer as a seed crystal, so that a crystalline semiconductor layer is formed. A semiconductor device having an n-channel transistor and a p-channel transistor formed with use of the crystalline semiconductor layer is provided.

摘要翻译： 在绝缘面上形成顶面与{211}面成±10°以内的岛状单晶半导体层， 形成与单晶半导体层的顶表面和侧表面以及绝缘表面接触的非单晶半导体层; 用激光照射非单晶半导体层以熔化非单晶半导体层，并且使用单晶半导体层将形成在绝缘表面上的非单晶半导体层结晶为 晶种，从而形成结晶半导体层。 提供了具有使用晶体半导体层形成的n沟道晶体管和p沟道晶体管的半导体器件。

公开(公告)号：US20100032667A1

公开(公告)日：2010-02-11

申请号：US12535714

申请日：2009-08-05

申请人： Shunpei YAMAZAKI ,  Hidekazu MIYAIRI ,  Akiharu MIYANAGA ,  Kengo AKIMOTO ,  Kojiro SHIRAISHI

发明人： Shunpei YAMAZAKI ,  Hidekazu MIYAIRI ,  Akiharu MIYANAGA ,  Kengo AKIMOTO ,  Kojiro SHIRAISHI

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/7869 ,  H01L29/78618

摘要： One of the objects of the present invention is to provide a thin film transistor using an oxide semiconductor film containing indium (In), gallium (Ga), and zinc (Zn), in which the contact resistance between the oxide semiconductor layer and a source and drain electrodes is reduced, and to provide a method for manufacturing the thin film transistor. An ohmic contact is formed by intentionally providing a buffer layer having a higher carrier concentration than the IGZO semiconductor layer between the IGZO semiconductor layer and the source and drain electrode layers.

摘要翻译： 本发明的目的之一是提供一种使用含有铟（In），镓（Ga）和锌（Zn））的氧化物半导体膜的薄膜晶体管，其中氧化物半导体层和源极之间的接触电阻 并且减少了漏电极，并且提供了制造薄膜晶体管的方法。 通过有意地提供具有比IGZO半导体层和源极和漏极电极层之间的IGZO半导体层更高的载流子浓度的缓冲层来形成欧姆接触。

公开(公告)号：US20110084264A1

公开(公告)日：2011-04-14

申请号：US12897160

申请日：2010-10-04

申请人： Shunpei YAMAZAKI ,  Masayuki SAKAKURA ,  Akiharu MIYANAGA ,  Masahiro TAKAHASHI ,  Takuya HIROHASHI ,  Takashi SHIMAZU

发明人： Shunpei YAMAZAKI ,  Masayuki SAKAKURA ,  Akiharu MIYANAGA ,  Masahiro TAKAHASHI ,  Takuya HIROHASHI ,  Takashi SHIMAZU

IPC分类号： H01L29/12

CPC分类号： H01L29/7869 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78693 ,  H01L29/78696

摘要： An object is to provide an oxide semiconductor layer having a novel structure which is preferably used for a semiconductor device. Alternatively, another object is to provide a semiconductor device using an oxide semiconductor layer having the novel structure. An oxide semiconductor layer includes an amorphous region which is mainly amorphous and a crystal region containing crystal grains of In2Ga2ZnO7 in a vicinity of a surface, in which the crystal grains are oriented so that the c-axis is almost vertical with respect to the surface. Alternatively, a semiconductor device uses such an oxide semiconductor layer.

摘要翻译： 目的在于提供一种具有新的结构的氧化物半导体层，其优选用于半导体器件。 或者，另一个目的是提供一种使用具有新颖结构的氧化物半导体层的半导体器件。 氧化物半导体层包括主要为非晶质的非晶区域和在表面附近含有In2Ga2ZnO7晶体的晶体区域，其中晶粒取向为使得c轴相对于表面几乎垂直。 或者，半导体器件使用这种氧化物半导体层。

公开(公告)号：US20100295046A1

公开(公告)日：2010-11-25

申请号：US12849964

申请日：2010-08-04

申请人： Shunpei YAMAZAKI ,  Hisashi OHTANI ,  Toru MITSUKI ,  Akiharu MIYANAGA ,  Yasushi OGATA

发明人： Shunpei YAMAZAKI ,  Hisashi OHTANI ,  Toru MITSUKI ,  Akiharu MIYANAGA ,  Yasushi OGATA

IPC分类号： H01L29/786

CPC分类号： H01L29/78675 ,  G02F1/13454 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/02664 ,  H01L21/02667 ,  H01L21/02672 ,  H01L21/3221 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/12 ,  H01L27/1277 ,  H01L29/04 ,  H01L29/66757 ,  H01L29/78654 ,  Y10S438/973

摘要： After an amorphous semiconductor thin film is crystallized by utilizing a catalyst element, the catalyst element is removed by performing a heat treatment in an atmosphere containing a halogen element. A resulting crystalline semiconductor thin film exhibits {110} orientation. Since individual crystal grains have approximately equal orientation, the crystalline semiconductor thin film has substantially no grain boundaries and has such crystallinity as to be considered a single crystal or considered so substantially.

摘要翻译： 在通过利用催化剂元素使无定形半导体薄膜结晶之后，通过在含有卤素元素的气氛中进行热处理来除去催化剂元素。 得到的晶体半导体薄膜显示{110}取向。 由于单个晶粒具有大致相等的取向，所以晶体半导体薄膜基本上不具有晶界，并且具有被认为是单晶的结晶度或者被认为是如此。

公开(公告)号：US20090267068A1

公开(公告)日：2009-10-29

申请号：US12429486

申请日：2009-04-24

申请人： Koji DAIRIKI ,  Hidekazu MIYAIRI ,  Toshiyuki ISA ,  Akiharu MIYANAGA ,  Takuya HIROHASHI ,  Shunpei YAMAZAKI ,  Takeyoshi WATABE

发明人： Koji DAIRIKI ,  Hidekazu MIYAIRI ,  Toshiyuki ISA ,  Akiharu MIYANAGA ,  Takuya HIROHASHI ,  Shunpei YAMAZAKI ,  Takeyoshi WATABE

IPC分类号： H01L29/786

CPC分类号： H01L27/127 ,  H01J37/32091 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/1288 ,  H01L29/04 ,  H01L29/66765 ,  H01L29/78669 ,  H01L29/78678 ,  H01L29/78696

摘要： The thin film transistor includes a gate insulating layer covering a gate electrode, over a substrate having an insulating surface; a semiconductor layer forming a channel formation region, in which a plurality of crystal regions is included in an amorphous structure; an impurity semiconductor layer imparting one conductivity type which forms a source region and a drain region; and a buffer layer formed from an amorphous semiconductor, which is located between the semiconductor layer and the impurity semiconductor layer. The thin film transistor includes the crystal region which includes minute crystal grains and inverted conical or inverted pyramidal grain each of which grows approximately radially from a position away from an interface between the gate insulating layer and the semiconductor layer toward a direction in which the semiconductor layer is deposited in a region which does not reach the impurity semiconductor layer.

摘要翻译： 薄膜晶体管包括覆盖栅电极的栅极绝缘层，在具有绝缘表面的基板上; 形成在非晶结构中包含多个晶体区域的沟道形成区域的半导体层; 赋予形成源极区域和漏极区域的一种导电型的杂质半导体层; 以及由位于半导体层和杂质半导体层之间的非晶半导体形成的缓冲层。 薄膜晶体管包括晶体区域，其包括微小晶粒和倒圆锥形或倒棱锥晶粒，其每个从远离栅极绝缘层和半导体层之间的界面的位置朝向半导体层的方向大致径向地生长 沉积在不到达杂质半导体层的区域中。

公开(公告)号：US20120273780A1

公开(公告)日：2012-11-01

申请号：US13547377

申请日：2012-07-12

申请人： Shunpei YAMAZAKI ,  Hidekazu MIYAIRI ,  Akiharu MIYANAGA ,  Kengo AKIMOTO ,  Kojiro SHIRAISHI

发明人： Shunpei YAMAZAKI ,  Hidekazu MIYAIRI ,  Akiharu MIYANAGA ,  Kengo AKIMOTO ,  Kojiro SHIRAISHI

IPC分类号： H01L29/12

CPC分类号： H01L29/78618 ,  G02F1/133345 ,  G02F1/133528 ,  G02F1/134336 ,  G02F1/13439 ,  G02F1/136286 ,  G02F1/1368 ,  G02F1/167 ,  G02F2201/123 ,  G09G3/3674 ,  G09G2310/0286 ,  H01L27/1225 ,  H01L27/3262 ,  H01L29/247 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696

摘要： An embodiment is to include an inverted staggered (bottom gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.

摘要翻译： 一个实施例是包括反向交错（底栅结构）薄膜晶体管，其中使用含有In，Ga和Zn的氧化物半导体膜作为半导体层，并且缓冲层设置在半导体层与源极和漏极之间 电极层。 有意地在源极和漏极电极层与半导体层之间提供具有比半导体层高的载流子浓度的缓冲层，从而形成欧姆接触。