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1.发明公开公开(公告)号：US20240321757A1
公开(公告)日：2024-09-26
申请号：US18733870
申请日：2024-06-05
发明人： Chuei-Tang Wang , Chen-Hua Yu , Chung-Shi Liu , Chih-Yuan Chang , Jiun-Yi Wu , Jeng-Shien Hsieh , Tin-Hao Kuo
IPC分类号： H01L23/538 , H01L21/48 , H01L21/683 , H01L23/00 , H01L23/31 , H01L25/065
CPC分类号： H01L23/5385 , H01L21/4853 , H01L21/6835 , H01L23/3128 , H01L23/5386 , H01L23/5387 , H01L24/20 , H01L24/24 , H01L24/82 , H01L25/0655 , H01L2224/24226 , H01L2224/82005 , H01L2924/3511
摘要： A manufacturing method of a semiconductor package is provided. The method includes: providing an initial rigid-flexible substrate, wherein the initial rigid-flexible substrate includes rigid structures and a flexible core laterally penetrating through the rigid structures, and further includes a supporting frame connected to the rigid structures; bonding a package structure onto the initial rigid-flexible substrate, wherein the package structure includes semiconductor dies and an encapsulant laterally surrounding the semiconductor dies; and removing the supporting frame.
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公开(公告)号：US20230378098A1
公开(公告)日：2023-11-23
申请号：US18362989
申请日：2023-08-01
发明人： Wei-Kang Hsieh , Hao-Yi Tsai , Tin-Hao Kuo , Shih-Wei Chen
IPC分类号： H01L23/00 , H01L23/31 , H01L23/538 , H01L21/683 , H01L21/48 , H01L21/56 , H01L25/00 , H01L23/40 , H01L25/065
CPC分类号： H01L23/562 , H01L23/3128 , H01L23/5383 , H01L23/5386 , H01L24/96 , H01L21/6835 , H01L21/4853 , H01L21/4857 , H01L21/561 , H01L21/565 , H01L21/568 , H01L25/50 , H01L23/4006 , H01L25/0655 , H01L2924/3511 , H01L2221/68372 , H01L2023/4031 , H01L2023/405 , H01L2023/4087 , H01L2224/95001
摘要： A semiconductor package has central region and peripheral region surrounding central region. The semiconductor package includes dies, encapsulant, and redistribution structure. The dies include functional die and first dummy dies. Functional die is disposed in central region. First dummy dies are disposed in peripheral region. Redistribution structure is disposed on encapsulant over the dies, and is electrically connected to functional die. Vacancy ratio of central region is in the range from 1.01 to 3.00. Vacancy ratio of the peripheral region is in the range from 1.01 to 3.00. Vacancy ratio of central region is a ratio of total area of central region to total area occupied by dies disposed in central region. Vacancy ratio of peripheral region is a ratio of total area of peripheral region to total area occupied by first dummy dies disposed in peripheral region.
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公开(公告)号：US11776905B2
公开(公告)日：2023-10-03
申请号：US17884548
申请日：2022-08-09
发明人： Chuei-Tang Wang , Tin-Hao Kuo
IPC分类号： H01L23/48 , H01L23/52 , H01L21/48 , H01L23/522 , H01L23/00 , H01L23/31 , H01L21/56 , H01L23/498
CPC分类号： H01L23/5226 , H01L21/486 , H01L21/4857 , H01L21/56 , H01L23/3121 , H01L23/49822 , H01L24/09 , H01L24/17 , H01L2224/02372 , H01L2924/15311
摘要： A package structure including an interposer, a semiconductor die, through insulator vias, an insulating encapsulant and a redistribution layer is provided. The interposer includes a core structure having a first and second surface, first metal layers disposed on the first and second surface, second metal layers disposed on the second surface over the first metal layers, and third metal layers disposed on the second surface over the second metal layers. The semiconductor die is disposed on the interposer. The through insulator vias are disposed on the interposer and electrically connected to the plurality of first metal layers. The insulating encapsulant is disposed on the interposer over the first surface and encapsulating the semiconductor die and the plurality of through insulator vias. The redistribution layer is disposed on the insulating encapsulant and electrically connected to the semiconductor die and the plurality of through insulator vias.
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公开(公告)号：US20230290731A1
公开(公告)日：2023-09-14
申请号：US18320203
申请日：2023-05-19
发明人： Kuo-Lung Pan , Hao-Yi Tsai , Tin-Hao Kuo
IPC分类号： H01L23/538 , H01L21/56 , H01L23/00 , H01L23/31 , H01L21/48 , H01L23/29 , H01L23/48 , H01L23/15 , H01L23/28 , H01L23/522 , H01L23/14 , H01L23/528
CPC分类号： H01L23/5389 , H01L21/568 , H01L23/562 , H01L23/3128 , H01L21/565 , H01L23/5386 , H01L24/20 , H01L24/19 , H01L21/4853 , H01L21/4857 , H01L23/5383 , H01L23/3107 , H01L23/3121 , H01L23/293 , H01L23/31 , H01L23/481 , H01L23/15 , H01L23/28 , H01L23/5226 , H01L23/147 , H01L23/522 , H01L23/528 , H01L23/3114 , H01L23/5283 , H01L2224/214 , H01L2924/3511 , H01L2924/35121
摘要： A chip package including a first semiconductor die, a support structure and a second semiconductor die is provided. The first semiconductor die includes a first dielectric layer and a plurality of conductive vias, the first dielectric layer includes a first region and a second region, the conductive vias is embedded in the first region of the first dielectric layer; a plurality of conductive pillars is disposed on and electrically connected to the conductive vias. The second semiconductor die is stacked over the support structure and the second region of the first dielectric layer; and an insulating encapsulant encapsulates the first semiconductor die, the second semiconductor die, the support structure and the conductive pillars, wherein the second semiconductor die is electrically connected to the first semiconductor die through the conductive pillars.
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公开(公告)号：US11682655B2
公开(公告)日：2023-06-20
申请号：US17222041
申请日：2021-04-05
发明人： Chen-Hua Yu , Ming Hung Tseng , Yen-Liang Lin , Tzu-Sung Huang , Tin-Hao Kuo , Hao-Yi Tsai
IPC分类号： H01L25/065 , H01L23/00 , H01L23/498 , H01L21/768 , H01L21/56 , H01L25/00 , H01L21/683 , H01L23/31 , H01L23/538 , H01L25/10
CPC分类号： H01L25/0657 , H01L21/56 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L21/76871 , H01L21/76877 , H01L23/3128 , H01L23/49816 , H01L23/49838 , H01L23/5389 , H01L24/05 , H01L24/06 , H01L24/14 , H01L24/19 , H01L24/20 , H01L25/105 , H01L25/50 , H01L21/563 , H01L23/3107 , H01L2221/68345 , H01L2221/68359 , H01L2221/68372 , H01L2224/0401 , H01L2224/04105 , H01L2224/05124 , H01L2224/12105 , H01L2224/214 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/73265 , H01L2224/73267 , H01L2224/92244 , H01L2225/0651 , H01L2225/06506 , H01L2225/06568 , H01L2225/1035 , H01L2225/1058 , H01L2924/15311 , H01L2224/73265 , H01L2224/32225 , H01L2224/48227 , H01L2924/00012 , H01L2224/73265 , H01L2224/32145 , H01L2224/48227 , H01L2924/00012 , H01L2224/48091 , H01L2924/00014
摘要： A method includes forming a first redistribution structure by depositing a first dielectric layer and forming first and second conductive features on the first dielectric layer, the second conductive feature being provided with a gap exposing the first dielectric layer. The method further includes depositing a second dielectric layer on the first and second conductive features; forming first and second openings in the second dielectric layer, the first opening exposing the first conductive feature and the second opening exposing the second conductive feature and the gap; forming a first via on the first conductive feature and partially in the first opening; forming a second via on the second conductive feature and partially in the second opening and the gap; attaching a die to the first redistribution structure adjacent the first via and the second via; and encapsulating the die, the first via, and the second via with an encapsulant.
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公开(公告)号：US11569202B2
公开(公告)日：2023-01-31
申请号：US17396773
申请日：2021-08-09
发明人： Tin-Hao Kuo , Chen-Hua Yu , Chung-Shi Liu , Hao-Yi Tsai , Yu-Chia Lai , Po-Yuan Teng
IPC分类号： H01L23/52 , H01L25/065 , H01L23/522 , H01L23/528 , H01L23/532 , H01L23/538 , H01L23/00 , H01L23/31 , H05K1/02 , H01L25/00
摘要： A semiconductor device, a circuit board structure and a manufacturing forming thereof are provided. A circuit board structure includes a core layer, a first build-up layer and a second build-up layer. The first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. The circuit board structure has a plurality of stress releasing trenches extending into the first build-up layer and the second build-up layer.
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公开(公告)号：US11538788B2
公开(公告)日：2022-12-27
申请号：US16180214
申请日：2018-11-05
发明人： Chen-Hua Yu , Kuo-Chung Yee , Hao-Yi Tsai , Tin-Hao Kuo
IPC分类号： H01L21/768 , H01L25/065 , H01L25/00 , H01L21/56 , H01L21/3105 , H01L23/48 , H01L23/528 , H01L23/00 , H01L23/367 , H01L23/31 , H01L23/538
摘要： A method includes forming a first through-via from a first conductive pad of a first device die, and forming a second through-via from a second conductive pad of a second device die. The first and second conductive pads are at top surfaces of the first and the second device dies, respectively. The first and the second conductive pads may be used as seed layers. The second device die is adhered to the top surface of the first device die. The method further includes encapsulating the first and the second device dies and the first and the second through-vias in an encapsulating material, with the first and the second device dies and the first and the second through-vias encapsulated in a same encapsulating process. The encapsulating material is planarized to reveal the first and the second through-vias. Redistribution lines are formed to electrically couple to the first and the second through-vias.
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公开(公告)号：US11532594B2
公开(公告)日：2022-12-20
申请号：US16418298
申请日：2019-05-21
发明人： Chen-Hua Yu , Kuo-Chung Yee , Hao-Yi Tsai , Tin-Hao Kuo
IPC分类号： H01L21/56 , H01L21/768 , H01L21/3105 , H01L25/065 , H01L25/00 , H01L23/48 , H01L23/528 , H01L23/00 , H01L23/367 , H01L23/31 , H01L23/538
摘要： A method includes forming a first through-via from a first conductive pad of a first device die, and forming a second through-via from a second conductive pad of a second device die. The first and second conductive pads are at top surfaces of the first and the second device dies, respectively. The first and the second conductive pads may be used as seed layers. The second device die is adhered to the top surface of the first device die. The method further includes encapsulating the first and the second device dies and the first and the second through-vias in an encapsulating material, with the first and the second device dies and the first and the second through-vias encapsulated in a same encapsulating process. The encapsulating material is planarized to reveal the first and the second through-vias. Redistribution lines are formed to electrically couple to the first and the second through-vias.
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公开(公告)号：US11424213B2
公开(公告)日：2022-08-23
申请号：US17017622
申请日：2020-09-10
发明人： Mao-Yen Chang , Chih-Wei Lin , Hao-Yi Tsai , Kuo-Lung Pan , Chun-Cheng Lin , Tin-Hao Kuo , Yu-Chia Lai , Chih-Hsuan Tai
IPC分类号： H01L23/00 , H01L25/00 , H01L21/56 , H01L23/538 , H01L25/18
摘要： A semiconductor structure includes a semiconductor wafer, a first surface mount component, a second surface mount component and a first barrier structure. The first surface mount component is disposed on the semiconductor wafer, and electrically connected to the semiconductor wafer through a plurality of first electrical connectors. The second surface mount component is disposed on the semiconductor wafer, and electrically connected to the semiconductor wafer through a plurality of second electrical connectors, wherein an edge of the second surface mount component is overhanging a periphery of the semiconductor wafer. The first barrier structure is disposed on the semiconductor wafer in between the second electrical connectors and the edge of the second surface mount component, wherein a first surface of the first barrier structure is facing the second electrical connectors, and a second surface of the first barrier structure is facing away from the second electrical connectors.
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公开(公告)号：US11417638B2
公开(公告)日：2022-08-16
申请号：US17023379
申请日：2020-09-17
发明人： Chi-Hui Lai , Chen-Hua Yu , Chung-Shi Liu , Hao-Yi Tsai , Tin-Hao Kuo
摘要： A semiconductor structure includes a semiconductor package and a connector. The semiconductor package includes a die and a redistribution structure. The redistribution structure is disposed over the die, and includes a plurality of conductive patterns stacking on one another and electrically connected to the die. The connector is disposed on the redistribution structure, and includes a connecting element. The connecting element penetrates the conductive patterns and is electrically connected to the die.
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