公开(公告)号：US4856754A

公开(公告)日：1989-08-15

申请号：US202108

申请日：1988-06-03

申请人： Takayoshi Yokota ,  Shigekazu Horiya ,  Sadao Uno ,  Kozo Katayama ,  Daijiro Tanabe

发明人： Takayoshi Yokota ,  Shigekazu Horiya ,  Sadao Uno ,  Kozo Katayama ,  Daijiro Tanabe

IPC分类号： B28B7/36 ,  E04G9/10

CPC分类号： B28B7/368 ,  E04G9/10

摘要： A shuttering used for forming concrete comprises a plate with a plurality of through holes opening on both its face and reverse, and a double woven fabric consisting of a face tissue which permits passage of water but prevents concrete from passing and a reverse tissue opposed to the face of the plate and relatively displaceable with respect to the face of the plate; the surplus water oozing out of placed concrete flows through gaps formed by the reverse tissue between said plate and the face tissue as well as the through holes of said plate.

公开(公告)号：US08017986B2

公开(公告)日：2011-09-13

申请号：US12718111

申请日：2010-03-05

申请人： Toshihiro Tanaka ,  Yukiko Umemoto ,  Mitsuru Hiraki ,  Yutaka Shinagawa ,  Masamichi Fujito ,  Kazufumi Suzukawa ,  Hiroyuki Tanikawa ,  Takashi Yamaki ,  Yoshiaki Kamigaki ,  Shinichi Minami ,  Kozo Katayama ,  Nozomu Matsuzaki

发明人： Toshihiro Tanaka ,  Yukiko Umemoto ,  Mitsuru Hiraki ,  Yutaka Shinagawa ,  Masamichi Fujito ,  Kazufumi Suzukawa ,  Hiroyuki Tanikawa ,  Takashi Yamaki ,  Yoshiaki Kamigaki ,  Shinichi Minami ,  Kozo Katayama ,  Nozomu Matsuzaki

IPC分类号： H01L29/788

CPC分类号： G11C16/26 ,  G11C5/025 ,  G11C8/08 ,  G11C16/04 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  H01L21/28 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/7885 ,  H01L29/792

摘要： A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc

摘要翻译： 半导体器件包括多个非易失性存储单元（1）。 每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。 第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。 第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。 第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。 假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

公开(公告)号：US07414283B2

公开(公告)日：2008-08-19

申请号：US11415129

申请日：2006-05-02

申请人： Toshihiro Tanaka ,  Yukiko Umemoto ,  Mitsuru Hiraki ,  Yutaka Shinagawa ,  Masamichi Fujito ,  Kazufumi Suzukawa ,  Hiroyuki Tanikawa ,  Takashi Yamaki ,  Yoshiaki Kamigaki ,  Shinichi Minami ,  Kozo Katayama ,  Nozomu Matsuzaki

发明人： Toshihiro Tanaka ,  Yukiko Umemoto ,  Mitsuru Hiraki ,  Yutaka Shinagawa ,  Masamichi Fujito ,  Kazufumi Suzukawa ,  Hiroyuki Tanikawa ,  Takashi Yamaki ,  Yoshiaki Kamigaki ,  Shinichi Minami ,  Kozo Katayama ,  Nozomu Matsuzaki

IPC分类号： H01L29/788

CPC分类号： G11C16/26 ,  G11C5/025 ,  G11C8/08 ,  G11C16/04 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  H01L21/28 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/7885 ,  H01L29/792

摘要： A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc

摘要翻译： 半导体器件包括多个非易失性存储单元（1）。 每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。 第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。 第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。 第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。 假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

公开(公告)号：US07190023B2

公开(公告)日：2007-03-13

申请号：US11320850

申请日：2005-12-30

申请人： Yoshiaki Kamigaki ,  Shinichi Minami ,  Kozo Katayama ,  Masataka Kato

发明人： Yoshiaki Kamigaki ,  Shinichi Minami ,  Kozo Katayama ,  Masataka Kato

IPC分类号： H01L29/788

CPC分类号： G11C16/0475 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42332 ,  H01L29/7887

摘要： A multi-storage nonvolatile memory of high density, high speed and high reliability has a memory transistor and switch transistors disposed on both the sides of the memory transistor. The memory transistor includes a gate insulating film having discrete traps and a memory gate electrode, whereas the switch transistors include switch gate electrodes. The gate insulating film has the discrete traps for storing information charge, can locally inject carriers, and one memory cell constitutes a multi-storage cell for storing at least information of 2 bits. The switch transistors having the switch gate electrodes realize source side injection. The memory transistor is fommed together with the switch transistors in self-aligned diffusion. The memory gate electrode of the memory transistor is connected to a word line so as to perform word-line erase.

摘要翻译： 高密度，高速度和高可靠性的多存储非易失性存储器具有置于存储晶体管的两侧的存储晶体管和开关晶体管。 存储晶体管包括具有离散陷阱和存储栅电极的栅极绝缘膜，而开关晶体管包括开关栅电极。 栅极绝缘膜具有用于存储信息电荷的离散陷阱，可以局部注入载流子，并且一个存储器单元构成用于至少存储2位信息的多存储单元。 具有开关栅电极的开关晶体管实现源极侧注入。 存储晶体管与自对准扩散中的开关晶体管一起发生。 存储晶体管的存储栅电极连接到字线，以便执行字线擦除。

公开(公告)号：US5258625A

公开(公告)日：1993-11-02

申请号：US961547

申请日：1992-10-15

申请人： Shiroo Kamohara ,  Toru Toyabe ,  Kozo Katayama ,  Shuichi Yamamoto ,  Sigeo Ihara

发明人： Shiroo Kamohara ,  Toru Toyabe ,  Kozo Katayama ,  Shuichi Yamamoto ,  Sigeo Ihara

IPC分类号： H01L21/82 ,  H01L21/8232 ,  H01L21/8244 ,  H01L27/06 ,  H01L27/095 ,  H01L27/10 ,  H01L27/11 ,  H01L27/118 ,  H01L29/66 ,  H01L29/68 ,  H01L29/72 ,  H01L29/762 ,  H01L29/80 ,  H01L29/88 ,  H03K19/02

CPC分类号： B82Y10/00 ,  B82Y30/00 ,  H01L27/118 ,  H01L29/72 ,  H01L29/762 ,  H01L29/88 ,  H03K19/02 ,  Y10S977/937

摘要： An interband single-electron tunnel transistor utilizes an interband single-electron tunneling phenomenon between a valence band and a conduction band through a p-n junction. The transistor includes the combination of microcapacities as fundamental constituent elements each formed by joining a p-type semiconductor material doped with an impurity in the degree of concentration with which a Fermi level overlaps a valence band and an n-type semiconductor material doped with an impurity in the degree of concentration with which the Fermi level overlaps a conduction band. The microcapacity includes a p-n junction having a junction area with which interband electron tunneling is inhibited due to Coulomb blockade.

摘要翻译： 带间单电子隧道晶体管利用通过p-n结的价带和导带之间的带间单电子隧道现象。 晶体管包括作为基本构成元件的微电容的组合，其通过将掺杂有杂质的p型半导体材料以费米能级与价带重叠的浓度与掺杂有杂质的n型半导体材料接合而形成 在费米能级与导带重叠的浓度下。 微容量包括具有结区的p-n结，由于库仑阻挡，带间电子隧道被阻止。

公开(公告)号：US08050085B2

公开(公告)日：2011-11-01

申请号：US10521553

申请日：2002-08-29

申请人： Masatoshi Takahashi ,  Takanori Yamazoe ,  Kozo Katayama ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Hiroshi Watase ,  Takeo Kanai ,  Nobutaka Nagasaki

发明人： Masatoshi Takahashi ,  Takanori Yamazoe ,  Kozo Katayama ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Hiroshi Watase ,  Takeo Kanai ,  Nobutaka Nagasaki

IPC分类号： G11C7/10 ,  G11C11/40

CPC分类号： G07F7/1008 ,  G06Q20/341 ,  G06Q20/40975 ,  G07F7/084 ,  G11C11/005 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/16

摘要： A semiconductor processing device according to the invention includes a first non-volatile memory (21) for erasing stored information on a first data length unit, a second non-volatile memory (22) for erasing stored information on a second data length unit, and a central processing unit (2), and capable of inputting/outputting encrypted data from/to an outside. The first non-volatile memory is used for storing an encryption key to be utilized for encrypting the data. The second non-volatile memory is used for storing a program to be processed by the central processing unit. The non-volatile memories to be utilized for storing the program and for storing the encryption key are separated from each other, and the data lengths of the erase units of information to be stored in the non-volatile memories are defined separately. Therefore, the stored information can efficiently be erased before the execution of a processing of writing the program, and the stored information can be erased corresponding to the data length of a necessary processing unit in the write of the encryption key to be utilized in the calculation processing of the CPU.

摘要翻译： 根据本发明的半导体处理装置包括用于擦除第一数据长度单元上存储的信息的第一非易失性存储器（21），用于擦除第二数据长度单元上存储的信息的第二非易失性存储器（22），以及 中央处理单元（2），能够从/向外部输入/输出加密数据。 第一非易失性存储器用于存储要用于加密数据的加密密钥。 第二非易失性存储器用于存储要由中央处理单元处理的程序。 用于存储程序和用于存储加密密钥的非易失性存储器彼此分离，并且存储在非易失性存储器中的信息的擦除单元的数据长度被分开地定义。 因此，在执行写入程序的处理之前可以有效地擦除存储的信息，并且可以根据在计算中要使用的加密密钥的写入中的必要处理单元的数据长度来擦除存储的信息 处理CPU。

公开(公告)号：US20090213649A1

公开(公告)日：2009-08-27

申请号：US10521553

申请日：2002-08-29

申请人： Masatoshi Takahashi ,  Takanori Yamazoe ,  Kozo Katayama ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Hiroshi Watase ,  Takeo Kanai ,  Nobutaka Nagasaki

发明人： Masatoshi Takahashi ,  Takanori Yamazoe ,  Kozo Katayama ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Hiroshi Watase ,  Takeo Kanai ,  Nobutaka Nagasaki

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C5/14 ,  G06F12/14

CPC分类号： G07F7/1008 ,  G06Q20/341 ,  G06Q20/40975 ,  G07F7/084 ,  G11C11/005 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/16

摘要： A semiconductor processing device according to the invention includes a first non-volatile memory (21) for erasing stored information on a first data length unit, a second non-volatile memory (22) for erasing stored information on a second data length unit, and a central processing unit (2), and capable of inputting/outputting encrypted data from/to an outside. The first non-volatile memory is used for storing an encryption key to be utilized for encrypting the data. The second non-volatile memory is used for storing a program to be processed by the central processing unit. The non-volatile memories to be utilized for storing the program and for storing the encryption key are separated from each other, and the data lengths of the erase units of information to be stored in the non-volatile memories are defined separately. Therefore, the stored information can efficiently be erased before the execution of a processing of writing the program, and the stored information can be erased corresponding to the data length of a necessary processing unit in the write of the encryption key to be utilized in the calculation processing of the CPU.

摘要翻译： 根据本发明的半导体处理装置包括用于擦除第一数据长度单元上存储的信息的第一非易失性存储器（21），用于擦除第二数据长度单元上存储的信息的第二非易失性存储器（22），以及 中央处理单元（2），能够从/向外部输入/输出加密数据。 第一非易失性存储器用于存储要用于加密数据的加密密钥。 第二非易失性存储器用于存储要由中央处理单元处理的程序。 用于存储程序和用于存储加密密钥的非易失性存储器彼此分离，并且存储在非易失性存储器中的信息的擦除单元的数据长度被分开地定义。 因此，在执行写入程序的处理之前可以有效地擦除存储的信息，并且可以根据在计算中要使用的加密密钥的写入中的必要处理单元的数据长度来擦除存储的信息 处理CPU。

公开(公告)号：US20060102967A1

公开(公告)日：2006-05-18

申请号：US11320850

申请日：2005-12-30

申请人： Yoshiaki Kamigaki ,  Shinichi Minami ,  Kozo Katayama ,  Masataka Kato

发明人： Yoshiaki Kamigaki ,  Shinichi Minami ,  Kozo Katayama ,  Masataka Kato

IPC分类号： H01L29/76

CPC分类号： G11C16/0475 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42332 ,  H01L29/7887

摘要： A multi-storage nonvolatile memory of high density, high speed and high reliability has a memory transistor and switch transistors disposed on both the sides of the memory transistor. The memory transistor includes a gate insulating film having discrete traps and a memory gate electrode, whereas the switch transistors include switch gate electrodes. The gate insulating film has the discrete traps for storing information charge, can locally inject carriers, and one memory cell constitutes a multi-storage cell for storing at least information of 2 bits. The switch transistors having the switch gate electrodes realize source side injection. The memory transistor is fommed together with the switch transistors in self-aligned diffusion. The memory gate electrode of the memory transistor is connected to a word line so as to perform word-line erase.

公开(公告)号：US06936888B2

公开(公告)日：2005-08-30

申请号：US10676158

申请日：2003-10-02

申请人： Kozo Katayama ,  Yoshiaki Kamigaki ,  Shinichi Minami

发明人： Kozo Katayama ,  Yoshiaki Kamigaki ,  Shinichi Minami

IPC分类号： B42D15/10 ,  G06K19/07 ,  G06K19/077 ,  G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76

CPC分类号： H01L27/115 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L29/7923

摘要： A nonvolatile memory device has a plurality of nonvolatile memory cells in which a memory gate electrode is formed over a first semiconductor region with a gate insulating film and a gate nitride film interposed therebetween. First and second switch gate electrodes, and first and second signal electrodes used as source/drain electrodes are formed on both sides of the memory gate electrode. Electrons are injected into the gate nitride film from the source side to store information in the memory cells. The memory gate electrode and the switch gate electrodes extend in the same direction. The application of a high electric field to a memory cell which is not selected for writing can be avoided owing to the switch gate electrodes being held in a cut-off state.

摘要翻译： 非易失性存储器件具有多个非易失性存储单元，其中存储栅极电极形成在第一半导体区域上，栅极绝缘膜和栅极氮化物膜介于其间。 第一和第二开关栅电极以及用作源/漏电极的第一和第二信号电极形成在存储栅电极的两侧。 从源极将电子注入到栅极氮化物膜中，以将信息存储在存储单元中。 存储栅电极和开关栅电极沿相同方向延伸。 由于开关栅极被保持在截止状态，因此可以避免对未被选择用于写入的存储单元施加高电场。

公开(公告)号：US06873009B2

公开(公告)日：2005-03-29

申请号：US10459621

申请日：2003-06-12

申请人： Dai Hisamoto ,  Kozo Katayama

发明人： Dai Hisamoto ,  Kozo Katayama

IPC分类号： G11C11/404 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/06 ,  H01L27/108 ,  H01L27/12 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L29/0895 ,  G11C11/404 ,  H01L21/823487 ,  H01L27/0688 ,  H01L27/108 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/1203

摘要： It is an object of the present invention to provides a field effect transistor with extremely low leakage current. It is another object of the invention to provide a semiconductor memory device having an excellent information holding characteristic. It is a further object of the invention to provide a method for manufacturing in a simple manner a novel field effect transistor or semiconductor memory device with extremely low leakage current. According to a typical basic configuration of the present invention, a thin insulating film is inserted in a vertically disposed Schottky junction to form source and drain electrodes and a tunnel of the insulating film in the junction is controlled by a gate electrode. The gate electrode is disposed on each of both sides of a vertical channel, permitting a field effect to be exerted effectively on the junction, whereby a junction leakage in an OFF state can be made extremely low.

摘要翻译： 本发明的目的是提供具有极低泄漏电流的场效应晶体管。 本发明的另一个目的是提供一种具有优异信息保持特性的半导体存储器件。 本发明的另一个目的是提供一种以简单的方式制造具有极低泄漏电流的新型场效晶体管或半导体存储器件的方法。 根据本发明的典型基本结构，将薄的绝缘膜插入垂直布置的肖特基结中以形成源极和漏极，并且在结中的绝缘膜的隧道由栅电极控制。 栅电极设置在垂直沟道的两侧中的每一侧上，从而能够有效地对接合部施加场效应，从而可以使断开状态下的结泄漏极低。