公开(公告)号：US20160163591A1

公开(公告)日：2016-06-09

申请号：US14561331

申请日：2014-12-05

Applicant: TOKYO ELECTRON LIMITED

Inventor： Tadahiro ISHIZAKA ,  Takashi SAKUMA ,  Osamu YOKOYAMA ,  Kai-Hung YU

IPC: H01L21/768 ,  H01L23/532 ,  C23C14/34 ,  C23C16/52 ,  C23C14/24 ,  C23C14/54 ,  H01L21/285 ,  H01L23/528

CPC classification number: C23C14/34 ,  C23C14/046 ,  C23C14/165 ,  C23C14/24 ,  C23C14/54 ,  C23C16/52 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76846 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A Cu wiring forming method of forming Cu wiring that is to be arranged in contact with tungsten wiring, by filling Cu into a recess formed in a substrate, includes: removing a tungsten oxide formed on a surface of the tungsten wiring; forming a nitriding preventing film at least on the surface of the tungsten wiring in the recess; forming a barrier film that prevents diffusion of Cu, on a surface in the recess from above the nitriding preventing film; forming a liner film on the barrier film; and filling a Cu film on the liner film.

Abstract translation: 通过将Cu填充到形成在基板中的凹部中，形成与钨布线接触而布置的Cu布线的Cu布线形成方法包括：去除形成在钨布线的表面上的氧化钨; 至少在所述凹部中的所述钨线的表面上形成防氮膜; 形成阻止膜从氮化防止膜上方阻止在凹部的表面上的扩散的阻挡膜; 在阻挡膜上形成衬垫膜; 并在衬膜上填充Cu膜。

公开(公告)号：US20150262872A1

公开(公告)日：2015-09-17

申请号：US14642331

申请日：2015-03-09

Applicant: TOKYO ELECTRON LIMITED

Inventor： Tadahiro ISHIZAKA ,  Takashi SAKUMA ,  Osamu YOKOYAMA ,  Kenji MATSUMOTO ,  Peng CHANG ,  Hiroyuki NAGAI

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/285

CPC classification number: H01L21/76877 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76876 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a copper wiring buried in a recess portion of a predetermined pattern formed in an interlayer insulation layer of a substrate is disclosed. The method includes: forming a manganese oxide film at least on a surface of the recess portion, the manganese oxide film serving as a self-aligned barrier film through reaction with the interlayer insulation layer; performing hydrogen radical treatment with respect to a surface of the manganese oxide film; placing a metal more active than ruthenium on the surface of the manganese oxide film after the hydrogen radical treatment; forming a ruthenium film on the surface where the metal more active than ruthenium is present; and forming a copper film on the ruthenium film by physical vapor deposition (PVD) to bury the copper film in the recess portion.

Abstract translation: 公开了一种埋设在衬底的层间绝缘层中形成的预定图案的凹部中的铜布线的形成方法。 该方法包括：通过与层间绝缘层反应，至少在凹部的表面上形成氧化锰膜，氧化锰膜作为自对准阻挡膜; 相对于氧化锰膜的表面进行氢自由基处理; 在氧自由基处理之后，将比钌更金属的氧化物膜置于氧化锰膜的表面上; 在其上存在比钌更有活性的金属的表面上形成钌膜; 并通过物理气相沉积（PVD）在钌膜上形成铜膜以将铜膜埋入凹部中。

公开(公告)号：US20230094053A1

公开(公告)日：2023-03-30

申请号：US17934668

申请日：2022-09-23

Applicant: Tokyo Electron Limited

Inventor： Yuichiro WAGATSUMA ,  Masahisa WATANABE ,  Mayuko NAKAMURA ,  TAKASHI SAKUMA ,  Osamu YOKOYAMA ,  Kwangpyo CHOI

IPC: H01L21/02 ,  H01L21/306

Abstract: A substrate processing method includes: preparing a substrate which includes a base having an epitaxial layer formed by epitaxial growth, and an insulating film formed on the base and having a penetration portion that exposes the epitaxial layer; forming a silicon film on a surface of the epitaxial layer exposed from the penetration portion rather than a side wall of the penetration portion; and forming a metal film on the silicon film formed on the surface of the epitaxial layer rather than the side wall of the penetration portion, and causing the silicon film to react with the metal film to form a metal silicide film.

公开(公告)号：US20160276218A1

公开(公告)日：2016-09-22

申请号：US15072165

申请日：2016-03-16

Applicant: Tokyo Electron Limited

Inventor： Kenji MATSUMOTO ,  Tadahiro ISHIZAKA ,  Peng CHANG ,  Osamu YOKOYAMA ,  Takashi SAKUMA ,  Hiroyuki NAGAI

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L23/53238 ,  H01L21/28556 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843

Abstract: In a Cu wiring manufacturing method, a MnOx film which becomes a self-formed barrier film by reaction with an interlayer insulating film of a substrate is formed on a surface of a recess formed in the interlayer insulating film by ALD. A hydrogen radical process is performed on a surface of the MnOx film to reduce the surface of the MnOx film. A Ru film is formed by CVD on the surface of the MnOx film which has been reduced by the hydrogen radical process. A Cu-based film is formed on the Ru film by PVD to be filled in the recess. When the Ru film is formed, a film-formation condition of the MnOx film and a condition of the hydrogen radical process are set such that nucleus formation is facilitated and the Ru film is formed in a state where a surface smoothness is high.

Abstract translation: 在Cu布线制造方法中，通过ALD形成在层间绝缘膜的凹部的表面上，形成通过与基板的层间绝缘膜反应而成为自形成的阻挡膜的MnO x膜。 在MnO x膜的表面上进行氢自由基处理以减少MnO x膜的表面。 在通过氢自由基还原的MnO x膜的表面上通过CVD形成Ru膜。 通过PVD在Ru膜上形成Cu基膜以填充在凹部中。 当形成Ru膜时，设定MnO x膜的成膜条件和氢自由基工艺的条件，使得形成核容易，并且在表面光滑度高的状态下形成Ru膜。

公开(公告)号：US20150332961A1

公开(公告)日：2015-11-19

申请号：US14701555

申请日：2015-05-01

Applicant: TOKYO ELECTRON LIMITED

Inventor： Tadahiro ISHIZAKA ,  Tatsuo HIRASAWA ,  Takashi SAKUMA ,  Osamu YOKOYAMA

IPC: H01L21/768

CPC classification number: H01L21/76882 ,  H01L21/2855 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76883

Abstract: Cu wiring fabrication method for fabricating Cu wiring with respect to substrate having interlayer dielectric film having trench formed thereon, includes: forming barrier film on surface of the trench; forming Ru film on surface of the barrier film by CVD; burying the trench by forming Cu film or Cu alloy film on the Ru film; forming Cu film or Cu alloy film at corners of bottom of the trench while re-sputtering the formed Cu film or Cu alloy film in a condition where first formed Cu film or Cu alloy film re-sputtered by an ion action of the plasma generation gas; and subsequently burying the Cu film or the Cu alloy film in the trench in condition where the Cu film or the Cu alloy film is formed on field portion of the substrate, and reflows in the trench by an ion action of the plasma generation gas.

Abstract translation: 涉及在其上形成有沟槽的具有沟槽的层间绝缘膜的衬底制造Cu布线的Cu布线制造方法包括：在沟槽的表面上形成阻挡膜; 通过CVD在阻挡膜的表面上形成Ru膜; 通过在Ru膜上形成Cu膜或Cu合金膜来掩埋沟槽; 在沟槽底部的角落处形成Cu膜或Cu合金膜，同时在通过等离子体发生气体的离子作用重新溅射的第一次形成的Cu膜或Cu合金膜的条件下再溅射形成的Cu膜或Cu合金膜 ; 并且随后在衬底的场部形成Cu膜或Cu合金膜的状态下将Cu膜或Cu合金膜埋入沟槽中，并且通过等离子体产生气体的离子作用在沟槽中回流。

公开(公告)号：US20140287163A1

公开(公告)日：2014-09-25

申请号：US14297726

申请日：2014-06-06

Applicant: TOKYO ELECTRON LIMITED

Inventor： Tadahiro ISHIZAKA ,  Atsushi GOMI ,  Takara FUKUSHIMA ,  Osamu YOKOYAMA ,  Takashi SAKUMA ,  Chiaki YASUMURO ,  Hiroyuki TOSHIMA ,  Tatsuo HATANO ,  Yasushi MIZUSAWA ,  Masamichi HARA ,  Kenzi SUZUKI

IPC: H01L21/02

CPC classification number: H01L21/02104 ,  C23C14/025 ,  C23C14/046 ,  C23C14/345 ,  C23C14/541 ,  C23C14/5806 ,  C23C16/16 ,  H01J37/32899 ,  H01J37/34

Abstract: A method of forming a Cu wiring in a trench or hole formed in a substrate is provided. The method includes forming a barrier film on the surface of the trench or hole, forming a Ru film on the barrier film, and embedding Cu in the trench or hole by forming a Cu film on the Ru film using PVD while annealing the substrate such that migration of copper into the trench or hole occurs.

Abstract translation: 提供了一种在衬底中形成的沟槽或孔中形成Cu布线的方法。 该方法包括在沟槽或孔的表面上形成阻挡膜，在阻挡膜上形成Ru膜，并且通过在使衬底退火的同时在PVD膜上形成Cu膜而将Cu嵌入沟槽或孔中，使得 发生铜进入沟槽或孔的迁移。

公开(公告)号：US20140090597A1

公开(公告)日：2014-04-03

申请号：US14044659

申请日：2013-10-02

Applicant: TOKYO ELECTRON LIMITED

Inventor： Tatsuo HIRASAWA ,  Osamu YOKOYAMA ,  Chiaki YASUMURO ,  Toshiaki FUJISATO ,  Ryota YOSHIDA ,  Takashi SAKUMA ,  Cheonsoo HAN

IPC: H05F3/00 ,  C23C16/50

CPC classification number: H05F3/00 ,  C23C14/34 ,  C23C14/50 ,  C23C16/50 ,  H01J37/32568 ,  H01J37/34 ,  H01L21/6833

Abstract: In a plasma processing method, plasma processing is performed in a state where the object is attracted and held on the electrostatic chuck by applying a first voltage as an application voltage thereto and a thermal conduction gas is supplied to a gap between the electrostatic chuck and the object. The application voltage is decreased while stopping the supply of the thermal conduction gas and exhausting the thermal conduction gas remaining between the electrostatic chuck and the object upon completion of the plasma processing. The object is separated from the electrostatic chuck by setting the application voltage to the electrostatic chuck to zero after the application voltage is decreased.

Abstract translation: 在等离子体处理方法中，通过施加第一电压作为施加电压，将物体吸附并保持在静电卡盘上的状态下进行等离子体处理，并且向静电卡盘和静电卡盘之间的间隙供给导热气体 目的。 在等离子体处理完成时，施加电压降低，同时停止供给导热气体并排出残留在静电卡盘与物体之间的导热气体。 在施加电压降低之后，通过将静电卡盘的施加电压设定为零将物体与静电卡盘分离。

公开(公告)号：US20170250086A1

公开(公告)日：2017-08-31

申请号：US15443687

申请日：2017-02-27

Applicant: TOKYO ELECTRON LIMITED

Inventor： Tomonari URANO ,  Kyohei NOGUCHI ,  Osamu YOKOYAMA ,  Takashi KOBAYASHI ,  Satoshi WAKABAYASHI ,  Takashi SAKUMA

IPC: H01L21/285 ,  H01L21/673 ,  H01L21/67

CPC classification number: H01L21/28556 ,  C23C16/08 ,  C23C16/34 ,  C23C16/4404 ,  C23C16/45542 ,  C23C16/45555 ,  H01L21/28518 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/67393 ,  H01L21/76843 ,  H01L21/76862

Abstract: A substrate processing method is for forming a metal film on a target substrate by using a plasma. The method includes loading a target substrate having a silicon-containing layer on a surface thereof into a processing chamber which is pre-coated by a film containing a metal, introducing hydrogen gas and a gaseous compound of the metal and halogen into the processing chamber, generating a plasma, and forming a metal film on the target substrate. The method further includes performing a first reduction process of forming an atmosphere of a plasma obtained by activating hydrogen gas in the processing chamber, unloading the target substrate from the processing chamber, performing a second reduction process of forming an atmosphere of a plasma obtained by activating hydrogen gas in the processing chamber, and loading a next target substrate into the processing chamber.

公开(公告)号：US20150004784A1

公开(公告)日：2015-01-01

申请号：US14316251

申请日：2014-06-26

Applicant: TOKYO ELECTRON LIMITED

Inventor： Osamu YOKOYAMA ,  Cheonsoo HAN ,  Takashi SAKUMA ,  Chiaki YASUMURO ,  Tatsuo HIRASAWA ,  Tadahiro ISHIZAKA ,  Kenji SUZUKI

IPC: H01L21/768

CPC classification number: H01L21/76877 ,  H01L21/2885 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76867 ,  H01L21/76876 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a method of forming a copper (Cu) wiring in a recess formed to have a predetermined pattern in an insulating film formed on a surface of a substrate. The method includes: forming a barrier film at least on a surface of the recess, the barrier film serving as a barrier for blocking diffusion of Cu; forming a Ru film on the barrier film by Chemical Mechanical Deposition (CVD); forming a Cu alloy film on the Ru film by Physical Vapor Deposition (PVD) to bury the recess; forming a Cu wiring using the Cu alloy film buried in the recess; and forming a dielectric film on the Cu wiring.

Abstract translation: 提供了在形成在基板表面上的绝缘膜中形成为具有预定图案的凹部中形成铜（Cu）布线的方法。 所述方法包括：至少在所述凹部的表面上形成阻挡膜，所述阻挡膜用作阻挡Cu的扩散的阻挡层; 通过化学机械沉积（CVD）在阻挡膜上形成Ru膜; 通过物理气相沉积（PVD）在Ru膜上形成Cu合金膜以埋藏凹槽; 使用埋在凹部中的Cu合金膜形成Cu布线; 并在Cu布线上形成电介质膜。