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    Wireless communication device
    1.
    发明申请
    Wireless communication device 审中-公开
    无线通信设备

    公开(公告)号：US20080189443A1

    公开(公告)日：2008-08-07

    申请号：US11700773

    申请日：2007-02-01

    申请人： Wei-Ming Chen ,  Yi-Cheng Yu ,  Chih-Tao Huang

    发明人： Wei-Ming Chen ,  Yi-Cheng Yu ,  Chih-Tao Huang

    IPC分类号： G06F3/00

    CPC分类号： G06F1/1698 ,  G06F1/1616 ,  G06F1/1656

    摘要： A wireless communication device includes an RF module, an audio-processing module, a receiving/transmitting module and a housing. The RF module connected wireless with a notebook computer is used for receiving/transmitting an RF data signal and converting the RF data signal into a respective digital audio signal. The audio-processing module is used to perform bi-directional conversion between digital audio signals and analog audio signals. The receiving/transmitting module is used to input or output the analog audio signals. The housing is used to integrate structurally the RF module, the audio-processing module and the receiving/transmitting module so as to appear the wireless communication device a size as a typical computer memory cartridge that can be accommodated inside a memory extension slot of the notebook computer.

    摘要翻译： 无线通信设备包括RF模块，音频处理模块，接收/发送模块和外壳。 用笔记本电脑无线连接的RF模块用于接收/发送RF数据信号，并将RF数据信号转换成相应的数字音频信号。 音频处理模块用于在数字音频信号和模拟音频信号之间执行双向转换。 接收/发送模块用于输入或输出模拟音频信号。 外壳用于结构化地结合RF模块，音频处理模块和接收/发送模块的集成，以将无线通信设备的尺寸显示为可以容纳在笔记本的存储器扩展槽内的典型的计算机存储盒 电脑。

    Electrical Fuse Structure and Method
    4.
    发明申请
    Electrical Fuse Structure and Method 审中-公开
    电气保险丝结构与方法

    公开(公告)号：US20100090751A1

    公开(公告)日：2010-04-15

    申请号：US12637510

    申请日：2009-12-14

    申请人： Hsin-Li Cheng ,  Chia-Jung Lee ,  Chin-Shan Hou ,  Wei-Ming Chen

    发明人： Hsin-Li Cheng ,  Chia-Jung Lee ,  Chin-Shan Hou ,  Wei-Ming Chen

    IPC分类号： H01H85/00 ,  H01L23/525

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： An electrical fuse and a process of programming the same are presented. An electrical fuse comprises a lower level silicide layer on a non-doped or lightly-doped polysilicon layer, an upper level conductive layer, and a tungsten contact coupled between the lower level silicide layer and the upper level conductive layer. The tungsten contact and a neck portion of the silicide layer are the programmable portion of the electrical fuse. High post-programming resistance is achieved by a first programming phase that depletes silicide in the silicide layer, followed by a second programming phase that depletes tungsten in the tungsten contact.

    摘要翻译： 介绍了电熔丝及其编程过程。 电熔丝包括在非掺杂或轻掺杂多晶硅层上的下层硅化物层，上层导电层和耦合在下层硅化物层和上层导电层之间的钨接触。 钨触点和硅化物层的颈部是电熔丝的可编程部分。 通过第一编程阶段实现高后编程电阻，其消耗硅化物层中的硅化物，随后是第二编程阶段，其消耗钨接触中的钨。

    Electrical fuse structure and method
    5.
    发明授权
    Electrical fuse structure and method 失效
    电熔丝结构及方法

    公开(公告)号：US07642176B2

    公开(公告)日：2010-01-05

    申请号：US12106759

    申请日：2008-04-21

    申请人： Hsin-Li Cheng ,  Chia-Jung Lee ,  Chin-Shan Hou ,  Wei-Ming Chen

    发明人： Hsin-Li Cheng ,  Chia-Jung Lee ,  Chin-Shan Hou ,  Wei-Ming Chen

    IPC分类号： H01L21/326 ,  H01L21/479

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： An electrical fuse and a process of programming the same are presented. An electrical fuse comprises a lower level silicide layer on a non-doped or lightly-doped polysilicon layer, an upper level conductive layer, and a tungsten contact coupled between the lower level silicide layer and the upper level conductive layer. The tungsten contact and a neck portion of the silicide layer are the programmable portion of the electrical fuse. High post-programming resistance is achieved by a first programming phase that depletes silicide in the silicide layer, followed by a second programming phase that depletes tungsten in the tungsten contact.

    摘要翻译： 介绍了电熔丝及其编程过程。 电熔丝包括在非掺杂或轻掺杂多晶硅层上的下层硅化物层，上层导电层和耦合在下层硅化物层和上层导电层之间的钨接触。 钨触点和硅化物层的颈部是电熔丝的可编程部分。 通过第一编程阶段实现高后编程电阻，其消耗硅化物层中的硅化物，随后是第二编程阶段，其消耗钨接触中的钨。

    Magnetic memory array
    6.
    发明授权
    Magnetic memory array 有权
    磁存储阵列

    公开(公告)号：US07349234B2

    公开(公告)日：2008-03-25

    申请号：US11119052

    申请日：2005-04-29

    申请人： Yuan-Ching Peng ,  Shyue-Shyh Lin ,  Wei-Ming Chen

    发明人： Yuan-Ching Peng ,  Shyue-Shyh Lin ,  Wei-Ming Chen

    IPC分类号： G11C5/08

    CPC分类号： G11C11/15 ,  G11C5/063

    摘要： A magnetic random access memory (MRAM) device disclosed herein includes an array of magnetic memory cells having magnetoresistive (MR) stacks. The MRAM array also includes a series of bit lines and word lines coupled to the MR stacks. The array layout provides for reduced crosstalk between neighboring memory cells by increasing a distance between neighboring MR stacks along a common conductor without increasing the overall layout area of the MRAM array. Several embodiments are disclosed where neighboring MR stacks are offset such that the MR stacks are staggered. For example, groups of MR stacks coupled to a common word line or to a common bit line can be staggered. The staggered layout provides for increased distance between neighboring MR stacks for a given MRAM array area, thereby resulting in a reduction of crosstalk, for example during write operations.

    摘要翻译： 本文公开的磁性随机存取存储器（MRAM）装置包括具有磁阻（MR）堆叠的磁存储器单元阵列。 MRAM阵列还包括耦合到MR堆叠的一系列位线和字线。 阵列布局通过增加沿着公共导体的相邻MR堆叠之间的距离而不增加MRAM阵列的总体布局面积来提供相邻存储器单元之间减少的串扰。 公开了几个实施例，其中相邻MR堆叠被偏移，使得MR堆叠交错。 例如，耦合到公共字线或公共位线的MR堆叠组可以交错。 交错布局提供了对于给定MRAM阵列区域的相邻MR堆叠之间的距离增加，从而导致例如在写入操作期间串扰的减少。

    Method for manufacturing, writing method and reading non-volatile memory
    7.
    发明申请
    Method for manufacturing, writing method and reading non-volatile memory 审中-公开
    制造方法，写入方法和读取非易失性存储器

    公开(公告)号：US20080043543A1

    公开(公告)日：2008-02-21

    申请号：US11889804

    申请日：2007-08-16

    申请人： Wei-Chung Chen ,  Ta-Neng Ho ,  Ti-Wen Chen ,  Wei-Ming Chen

    发明人： Wei-Chung Chen ,  Ta-Neng Ho ,  Ti-Wen Chen ,  Wei-Ming Chen

    IPC分类号： G11C7/00 ,  H01L21/266

    CPC分类号： G11C7/02 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1087

    摘要： A method of manufacturing, programming and reading a non-volatile memory is provided. First, a to-be-coded memory having a plurality of to-be-coded cells arranged in a array is provided. Next, an implanting resist layer is formed on the to-be-coded memory. Then, a mask is disposed on the to-be-coded memory, wherein the number of the partial to-be-coded cells under the openings of the mask is less than the number of remaining to-be-coded cells. Afterwards, a patterned implanting resist layer is formed according to the mask. Next, the exposed to-be-coded cells are ion-implanted to define a plurality of first cells and second cells, wherein each first cell and each second cell record a second bit state and a first bit state respectively. Then, the to-be-coded memory is inversely defined, such that the first cells and the second cells record the first bit state and the second bit state respectively.

    摘要翻译： 提供了制造，编程和读取非易失性存储器的方法。 首先，提供具有排列成阵列的多个被编码单元的被编码存储器。 接下来，在被编码存储器上形成植入抗蚀剂层。 然后，将掩模设置在待编码存储器上，其中掩模开口下部分待编码单元的数量小于剩余待编码单元的数量。 然后，根据掩模形成图案化的植入抗蚀剂层。 接下来，暴露的待编码单元被离子注入以限定多个第一单元和第二单元，其中每个第一单元和每个第二单元分别记录第二位状态和第一位状态。 然后，被编码的存储器被反向定义，使得第一单元和第二单元分别记录第一位状态和第二位状态。

    Method of calculating the real added defect counts
    8.
    发明授权
    Method of calculating the real added defect counts 有权
    计算真实附加缺陷计数的方法

    公开(公告)号：US06794203B2

    公开(公告)日：2004-09-21

    申请号：US10218591

    申请日：2002-08-15

    申请人： Wei-Ming Chen ,  Kun-Yu Liu ,  Chun-Chieh Chen ,  Lien-Che Ho

    发明人： Wei-Ming Chen ,  Kun-Yu Liu ,  Chun-Chieh Chen ,  Lien-Che Ho

    IPC分类号： H01L2166

    CPC分类号： H01L21/67288

    摘要： The present invention provides a method of producing an added defect count for monitoring the property of chambers or wafers. First, a proper pre-process sensitivity is determined with map to map process by maximizing the summation of a mapping rate and a catching rate. Second, a wafer is scanned with the proper pre-process sensitivity and a pre-process particle number P1 is recorded. Third, a manufacturing step is processed on the wafer. Fourth, the wafer is scanned with the most sensitive scale of the post-process sensitivities and a post-process particle number P2 is recorded. Finally, the post-process particle number P2 is subtracted from the pre-process particle number P1.

    摘要翻译： 本发明提供一种制造用于监测室或晶片的性质的附加缺陷计数的方法。 首先，通过最大化映射率和捕获率的总和，通过映射到映射过程来确定适当的预处理灵敏度。 其次，以适当的预处理灵敏度扫描晶片，并记录预处理颗粒数P1。 第三，在晶片上处理制造步骤。 第四，用最敏感的后处理灵敏度来扫描晶片，并记录后处理粒子数P2。 最后，从预处理粒子数P1中减去后处理粒子数P2。

    Method of generating multiple oxide thicknesses by one oxidation step using NH3 nitridation followed by re-oxidation
    9.
    发明授权
    Method of generating multiple oxide thicknesses by one oxidation step using NH3 nitridation followed by re-oxidation 有权
    通过一次氧化步骤使用NH3氮化再生氧化产生多个氧化物厚度的方法

    公开(公告)号：US06225167B1

    公开(公告)日：2001-05-01

    申请号：US09523988

    申请日：2000-03-13

    申请人： Mo-Chiun Yu ,  Wei-Ming Chen

    发明人： Mo-Chiun Yu ,  Wei-Ming Chen

    IPC分类号： H01L218234

    CPC分类号： H01L21/28185 ,  H01L21/0214 ,  H01L21/0223 ,  H01L21/02238 ,  H01L21/02247 ,  H01L21/02255 ,  H01L21/28167 ,  H01L21/28202 ,  H01L21/28238 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3144 ,  H01L21/31662 ,  H01L21/3185 ,  H01L21/3211 ,  H01L21/823462 ,  H01L27/112 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/518 ,  Y10S438/911

    摘要： A method is disclosed to form a plurality of oxides of different thicknesses with one step oxidation. In a first embodiment, a substrate is provided having a high-voltage cell area and a peripheral low-voltage logic area separated by a trench isolation region. The substrate is first nitrided. Then the nitride layer over the high-voltage area is removed, and the substrate is wet cleaned with HF solution. The substrate surface is next oxidized to form a tunnel oxide of desired thickness over the high-voltage. In a second embodiment, a sacrificial oxide is used over the substrate for patterning the high voltage cell area and the low-voltage logic area. The sacrificial oxide is removed from the low-voltage area and the substrate is nitrided after cleaning with a solution not containing HF, thus forming a nitride layer over the low-voltage area. Then, the sacrificial oxide is removed from the high-voltage area with an HF dip, and tunnel oxide of desired thickness is formed over the same area. In this manner, oxides of multiple thicknesses are provided for the high-voltage cell area and the low-voltage peripheral logic area with one oxidation step. At the same time, with a judicious use of cleaning and nitridation, any detrimental effects of the native oxide are circumvented.

    摘要翻译： 公开了通过一步氧化形成不同厚度的多个氧化物的方法。 在第一实施例中，提供了具有由沟槽隔离区域隔开的高压电池区域和外围低电压逻辑区域的衬底。 首先氮化基底。 然后去除高压区域上的氮化物层，并用HF溶液湿式清洗衬底。 接着氧化氧化衬底表面以在高电压下形成所需厚度的隧道氧化物。 在第二实施例中，在衬底上使用牺牲氧化物来构图高压电池区域和低电压逻辑区域。 从低电压区域除去牺牲氧化物，并且在用不含HF的溶液清洗之后将衬底氮化，从而在低电压区域上形成氮化物层。 然后，通过HF浸渍从高压区域去除牺牲氧化物，并且在相同的区域上形成所需厚度的隧道氧化物。 以这种方式，通过一个氧化步骤为高压电池区域和低电压外围逻辑区域提供多个厚度的氧化物。 同时，明智地使用清洁和氮化，可避免天然氧化物的任何有害影响。

    Method of making and accessing split gate memory device
    10.
    发明授权
    Method of making and accessing split gate memory device 失效
    制造和访问分闸门存储器件的方法

    公开(公告)号：US5824584A

    公开(公告)日：1998-10-20

    申请号：US876326

    申请日：1997-06-16

    申请人： Wei-Ming Chen ,  Lee Z. Wang ,  Kuo-Tung Chang ,  Craig Swift

    发明人： Wei-Ming Chen ,  Lee Z. Wang ,  Kuo-Tung Chang ,  Craig Swift

    IPC分类号： H01L21/8239 ,  H01L27/105 ,  H01L21/336

    CPC分类号： H01L27/105 ,  H01L27/1052 ,  Y10S438/933

    摘要： A non-volatile memory having a control gate (14) and a sidewall select gate (28) is illustrated. The sidewall select gate (28) is formed in conjunction with a semiconductor doped oxide (20) to form a non-volatile memory cell (7). The semiconductor element used to dope the oxide layer (20) will generally include silicon or germanium. The non-volatile memory cell (7) is programmed by storing electrons in the doped oxide (20), and is erased using band-to-band tunneling.

    摘要翻译： 示出了具有控制栅极（14）和侧壁选择栅极（28）的非易失性存储器。 侧壁选择栅极（28）与半导体掺杂氧化物（20）结合形成以形成非易失性存储单元（7）。 用于掺杂氧化物层（20）的半导体元件通常将包括硅或锗。 通过在掺杂氧化物（20）中存储电子来对非易失性存储单元（7）进行编程，并且使用带 - 带隧道进行擦除。