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公开(公告)号：US06423905B1
公开(公告)日：2002-07-23
申请号：US09562109
申请日：2000-05-01
IPC分类号： H05K103
CPC分类号： H05K3/4688 , H05K1/0271 , H05K3/429 , H05K2201/0133 , H05K2201/0195
摘要： A printed wiring board having a layered composite of metal planes and dielectric layers. At least one of the dielectric layers has a modulus lower than the modulus of the remaining dielectric material layers. A plating, extending through the layered composite, has a first land on a first external surface of the layered composite, a second land on a second external surface of the layered composite, and a barrel extending between the first land and the second land. The lower modulus dielectric material layer deforms during thermal excursions of the printed wiring board in such a way as to reduce the strains imposed on both the lands and the barrel of the plated through holes.
摘要翻译： 一种具有金属平面和电介质层的复合层的印刷电路板。 电介质层中的至少一个具有低于剩余介电材料层的模量的模量。 延伸穿过层状复合材料的电镀具有在层状复合材料的第一外表面上的第一焊盘，层状复合材料的第二外表面上的第二焊盘，以及在第一焊盘和第二焊盘之间延伸的镜筒。 在印刷线路板的热偏移期间，较低模量的介电材料层变形，以便减小施加在电镀通孔的焊盘和圆筒上的应变。
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公开(公告)号：US07185428B2
公开(公告)日：2007-03-06
申请号：US10738705
申请日：2003-12-16
IPC分类号： H05K3/02
CPC分类号： H05K3/06 , B32B15/08 , B32B15/20 , B32B27/04 , B32B27/06 , B32B27/30 , B32B27/38 , H01L21/32134 , H01L21/4846 , H01L21/76838 , H01L2924/0002 , H05K3/027 , H05K3/061 , H05K3/064 , H05K2203/0369 , H05K2203/1476 , Y10T29/49117 , Y10T29/49124 , Y10T29/49139 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165 , Y10T428/24322 , Y10T428/24802 , H01L2924/00
摘要： A circuitized substrate and a method of making the circuitized substrate is provided. The circuitized substrate includes a substrate having a substantially planar upper surface and a conductive layer positioned on the substantially planar upper surface. The conductive layer includes at least one side wall therein, defining an opening in the conductive layer. The conductive layer includes an end portion spaced from the opening, the end portion forming an acute angle with the substantially planar upper surface of the substrate. The at least one side wall is substantially perpendicular to the substantially planar upper surface of the substrate.
摘要翻译： 提供电路化基板和制造电路化基板的方法。 电路化基板包括具有基本平坦的上表面的基板和位于基本平坦的上表面上的导电层。 导电层包括其中的至少一个侧壁，在导电层中限定开口。 所述导电层包括与所述开口间隔开的端部，所述端部与所述基板的大致平坦的上表面形成锐角。 所述至少一个侧壁基本上垂直于所述基底的基本平坦的上表面。
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公开(公告)号：US06822332B2
公开(公告)日：2004-11-23
申请号：US10253439
申请日：2002-09-23
IPC分类号： H01L2348
CPC分类号： H05K3/06 , B32B15/08 , B32B15/20 , B32B27/04 , B32B27/06 , B32B27/30 , B32B27/38 , H01L21/32134 , H01L21/4846 , H01L21/76838 , H01L2924/0002 , H05K3/027 , H05K3/061 , H05K3/064 , H05K2203/0369 , H05K2203/1476 , Y10T29/49117 , Y10T29/49124 , Y10T29/49139 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165 , Y10T428/24322 , Y10T428/24802 , H01L2924/00
摘要： A circuitized substrate and a method of making the circuitized substrate is provided. The circuitized substrate includes a substrate having a substantially planar upper surface and a conductive layer positioned on the substantially planar upper surface. The conductive layer includes at least one side wall therein, defining an opening in the conductive layer. The conductive layer includes an end portion spaced from the opening, the end portion forming an acute angle with the substantially planar upper surface of the substrate. The at least one side wall is substantially perpendicular to the substantially planar upper surface of the substrate.
摘要翻译： 提供电路化基板和制造电路化基板的方法。 电路化基板包括具有基本平坦的上表面的基板和位于基本平坦的上表面上的导电层。 导电层包括其中的至少一个侧壁，在导电层中限定开口。 所述导电层包括与所述开口间隔开的端部，所述端部与所述基板的大致平坦的上表面形成锐角。 所述至少一个侧壁基本上垂直于所述基底的基本平坦的上表面。
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公开(公告)号：US07596862B2
公开(公告)日：2009-10-06
申请号：US11863820
申请日：2007-09-28
IPC分类号： H05K3/02
CPC分类号： H05K3/06 , B32B15/08 , B32B15/20 , B32B27/04 , B32B27/06 , B32B27/30 , B32B27/38 , H01L21/32134 , H01L21/4846 , H01L21/76838 , H01L2924/0002 , H05K3/027 , H05K3/061 , H05K3/064 , H05K2203/0369 , H05K2203/1476 , Y10T29/49117 , Y10T29/49124 , Y10T29/49139 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165 , Y10T428/24322 , Y10T428/24802 , H01L2924/00
摘要： A method of making the circuitized substrate. The circuitized substrate includes a substrate having a substantially planar upper surface and a conductive layer positioned on the substantially planar upper surface. The conductive layer includes at least one side wall therein, defining an opening in the conductive layer. The conductive layer includes an end portion spaced from the opening, the end portion forming an acute angle with the substantially planar upper surface of the substrate. The at least one side wall is substantially perpendicular to the substantially planar upper surface of the substrate.
摘要翻译： 制造电路化基板的方法。 电路化基板包括具有基本平坦的上表面的基板和位于基本平坦的上表面上的导电层。 导电层包括其中的至少一个侧壁，在导电层中限定开口。 所述导电层包括与所述开口间隔开的端部，所述端部与所述基板的大致平坦的上表面形成锐角。 所述至少一个侧壁基本上垂直于所述基底的基本平坦的上表面。
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公开(公告)号：US07325299B2
公开(公告)日：2008-02-05
申请号：US11619789
申请日：2007-01-04
CPC分类号： H05K3/06 , B32B15/08 , B32B15/20 , B32B27/04 , B32B27/06 , B32B27/30 , B32B27/38 , H01L21/32134 , H01L21/4846 , H01L21/76838 , H01L2924/0002 , H05K3/027 , H05K3/061 , H05K3/064 , H05K2203/0369 , H05K2203/1476 , Y10T29/49117 , Y10T29/49124 , Y10T29/49139 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165 , Y10T428/24322 , Y10T428/24802 , H01L2924/00
摘要： A method of making a circuitized substrate. A conductive layer having a substantially planar upper surface is formed on and in direct mechanical contact with an upper surface of a substrate. A portion of the conductive layer is removed to form an interim side wall in the conductive layer. A layer of patternable material is formed on the substantially planar upper surface and on the interim side wall. A portion of the layer of patternable material on the conductive layer is removed to expose the interim side wall. A portion of the substantially planar upper surface is removed to form a side wall in the layer of patternable material. Portions of the interim side wall in the conductive layer are removed to form a second side wall and a bottom wall defined by the upper surface of the substrate. The second side wall is substantially perpendicular to the bottom wall.
摘要翻译： 制造电路化基板的方法。 具有基本平坦的上表面的导电层形成在基板的上表面上并与基板的上表面直接机械接触。 去除导电层的一部分以在导电层中形成临时侧壁。 在基本平坦的上表面和临时侧壁上形成可图案化材料层。 去除导电层上图案化材料层的一部分以露出临时侧壁。 去除基本平坦的上表面的一部分以在可图案材料层中形成侧壁。 去除导电层中的临时侧壁的部分以形成由衬底的上表面限定的第二侧壁和底壁。 第二侧壁基本上垂直于底壁。
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公开(公告)号：US06962642B2
公开(公告)日：2005-11-08
申请号：US10255456
申请日：2002-09-26
申请人： Kevin T. Knadle , Anita Sargent
发明人： Kevin T. Knadle , Anita Sargent
CPC分类号： B32B15/08 , H05K3/386 , H05K2201/0329 , H05K2203/135 , Y10T29/49885
摘要： A process by which high frequency printed wiring board construction can be fabricated using smooth copper surfaces. A conductive, thin film polymer is plated on smooth copper surfaces of a core lamination. The polymer can be selected from a group of materials consisting of polypyrrole, polyaniline, polythiophene, and combinations thereof. The conductive polymer promotes adhesion between the resin polymer of the laminate and the smooth copper surfaces.
摘要翻译： 可以使用光滑的铜表面制造高频印刷线路板结构的方法。 将导电薄膜聚合物镀在芯片层压的光滑铜表面上。 聚合物可以选自由聚吡咯，聚苯胺，聚噻吩及其组合组成的一组材料。 导电聚合物促进层压体的树脂聚合物与光滑的铜表面之间的粘附。
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公开(公告)号：US07129732B1
公开(公告)日：2006-10-31
申请号：US11281456
申请日：2005-11-18
申请人： Kevin T. Knadle
发明人： Kevin T. Knadle
CPC分类号： G01R31/2817 , G01R31/2805
摘要： A test apparatus for testing circuitized substrates such as PCB test coupons for thru-hole failure in which the substrate may be cooled to a temperature less than the ambient temperature surrounding the test apparatus housing in which the testing is accomplished. A method of testing substrates is also provided.
摘要翻译： 用于测试电路化基板的测试装置，例如用于通孔故障的PCB测试试样，其中基板可以被冷却到低于其中完成测试的测试装置壳体周围的环境温度的温度。 还提供了测试基板的方法。
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公开(公告)号：US06931722B2
公开(公告)日：2005-08-23
申请号：US10395944
申请日：2003-03-24
申请人： Edward L. Arrington , Anilkumar C. Bhatt , Edmond O. Fey , Kevin T. Knadle , John J. Konrad , Joseph A Kotylo , Jeffrey McKeveny , Jose A. Rios , Amit K. Sarkhel , Andrew M. Seman , Timothy L. Wells
发明人： Edward L. Arrington , Anilkumar C. Bhatt , Edmond O. Fey , Kevin T. Knadle , John J. Konrad , Joseph A Kotylo , Jeffrey McKeveny , Jose A. Rios , Amit K. Sarkhel , Andrew M. Seman , Timothy L. Wells
CPC分类号： H05K3/243 , H05K3/28 , H05K3/3452 , H05K3/3473 , H05K3/42 , H05K2201/0391 , H05K2203/0315 , H05K2203/0574 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165
摘要： A method of fabricating a printed circuit device including an electrically insulating substrate, and first, second, and third sets of conductors formed on a top surface of the substrate is disclosed. The method includes forming an oxide layer on the set of second conductors; forming a solder mask on the oxide layer; forming a composite layer on the first set of conductors; and forming a solder layer on at least a portion of the third set of conductors.
摘要翻译： 公开了一种制造印刷电路器件的方法，该印刷电路器件包括电绝缘衬底以及形成在衬底顶表面上的第一组，第二组和第三组导体。 该方法包括在第二导体组上形成氧化物层; 在氧化物层上形成焊料掩模; 在第一组导体上形成复合层; 以及在所述第三组导体的至少一部分上形成焊料层。
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公开(公告)号：US06586683B2
公开(公告)日：2003-07-01
申请号：US09844814
申请日：2001-04-27
申请人： Edward L. Arrington , Anilkumar C. Bhatt , Edmond O. Fey , Kevin T. Knadle , John J. Konrad , Joseph A. Kotylo , Jeffrey McKeveny , Jose A. Rios , Amit K. Sarkhel , Andrew M. Seman , Timothy L. Wells
发明人： Edward L. Arrington , Anilkumar C. Bhatt , Edmond O. Fey , Kevin T. Knadle , John J. Konrad , Joseph A. Kotylo , Jeffrey McKeveny , Jose A. Rios , Amit K. Sarkhel , Andrew M. Seman , Timothy L. Wells
IPC分类号： H05K103
CPC分类号： H05K3/243 , H05K3/28 , H05K3/3452 , H05K3/3473 , H05K3/42 , H05K2201/0391 , H05K2203/0315 , H05K2203/0574 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165
摘要： A method of fabricating a printed circuit device including an electrically insulating substrate, and first, second, and third sets of conductors formed on a top surface of the substrate is disclosed. The method includes forming an oxide layer on the set of second conductors; forming a solder mask on the oxide layer; forming a composite layer on the first set of conductors; and forming a solder layer on at least a portion of the third set of conductors.
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