公开(公告)号：US07185428B2

公开(公告)日：2007-03-06

申请号：US10738705

申请日：2003-12-16

申请人： Frank D. Egitto ,  Kevin T. Knadle ,  Andrew M. Seman

发明人： Frank D. Egitto ,  Kevin T. Knadle ,  Andrew M. Seman

IPC分类号： H05K3/02

CPC分类号： H05K3/06 ,  B32B15/08 ,  B32B15/20 ,  B32B27/04 ,  B32B27/06 ,  B32B27/30 ,  B32B27/38 ,  H01L21/32134 ,  H01L21/4846 ,  H01L21/76838 ,  H01L2924/0002 ,  H05K3/027 ,  H05K3/061 ,  H05K3/064 ,  H05K2203/0369 ,  H05K2203/1476 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49139 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T428/24322 ,  Y10T428/24802 ,  H01L2924/00

摘要： A circuitized substrate and a method of making the circuitized substrate is provided. The circuitized substrate includes a substrate having a substantially planar upper surface and a conductive layer positioned on the substantially planar upper surface. The conductive layer includes at least one side wall therein, defining an opening in the conductive layer. The conductive layer includes an end portion spaced from the opening, the end portion forming an acute angle with the substantially planar upper surface of the substrate. The at least one side wall is substantially perpendicular to the substantially planar upper surface of the substrate.

摘要翻译： 提供电路化基板和制造电路化基板的方法。 电路化基板包括具有基本平坦的上表面的基板和位于基本平坦的上表面上的导电层。 导电层包括其中的至少一个侧壁，在导电层中限定开口。 所述导电层包括与所述开口间隔开的端部，所述端部与所述基板的大致平坦的上表面形成锐角。 所述至少一个侧壁基本上垂直于所述基底的基本平坦的上表面。

公开(公告)号：US06822332B2

公开(公告)日：2004-11-23

申请号：US10253439

申请日：2002-09-23

申请人： Frank D. Egitto ,  Kevin T. Knadle ,  Andrew M. Seman

发明人： Frank D. Egitto ,  Kevin T. Knadle ,  Andrew M. Seman

IPC分类号： H01L2348

CPC分类号： H05K3/06 ,  B32B15/08 ,  B32B15/20 ,  B32B27/04 ,  B32B27/06 ,  B32B27/30 ,  B32B27/38 ,  H01L21/32134 ,  H01L21/4846 ,  H01L21/76838 ,  H01L2924/0002 ,  H05K3/027 ,  H05K3/061 ,  H05K3/064 ,  H05K2203/0369 ,  H05K2203/1476 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49139 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T428/24322 ,  Y10T428/24802 ,  H01L2924/00

摘要： A circuitized substrate and a method of making the circuitized substrate is provided. The circuitized substrate includes a substrate having a substantially planar upper surface and a conductive layer positioned on the substantially planar upper surface. The conductive layer includes at least one side wall therein, defining an opening in the conductive layer. The conductive layer includes an end portion spaced from the opening, the end portion forming an acute angle with the substantially planar upper surface of the substrate. The at least one side wall is substantially perpendicular to the substantially planar upper surface of the substrate.

摘要翻译： 提供电路化基板和制造电路化基板的方法。 电路化基板包括具有基本平坦的上表面的基板和位于基本平坦的上表面上的导电层。 导电层包括其中的至少一个侧壁，在导电层中限定开口。 所述导电层包括与所述开口间隔开的端部，所述端部与所述基板的大致平坦的上表面形成锐角。 所述至少一个侧壁基本上垂直于所述基底的基本平坦的上表面。

公开(公告)号：US07596862B2

公开(公告)日：2009-10-06

申请号：US11863820

申请日：2007-09-28

申请人： Frank D. Egitto ,  Kevin T. Knadle ,  Andrew M. Seman

发明人： Frank D. Egitto ,  Kevin T. Knadle ,  Andrew M. Seman

IPC分类号： H05K3/02

CPC分类号： H05K3/06 ,  B32B15/08 ,  B32B15/20 ,  B32B27/04 ,  B32B27/06 ,  B32B27/30 ,  B32B27/38 ,  H01L21/32134 ,  H01L21/4846 ,  H01L21/76838 ,  H01L2924/0002 ,  H05K3/027 ,  H05K3/061 ,  H05K3/064 ,  H05K2203/0369 ,  H05K2203/1476 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49139 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T428/24322 ,  Y10T428/24802 ,  H01L2924/00

摘要： A method of making the circuitized substrate. The circuitized substrate includes a substrate having a substantially planar upper surface and a conductive layer positioned on the substantially planar upper surface. The conductive layer includes at least one side wall therein, defining an opening in the conductive layer. The conductive layer includes an end portion spaced from the opening, the end portion forming an acute angle with the substantially planar upper surface of the substrate. The at least one side wall is substantially perpendicular to the substantially planar upper surface of the substrate.

摘要翻译： 制造电路化基板的方法。 电路化基板包括具有基本平坦的上表面的基板和位于基本平坦的上表面上的导电层。 导电层包括其中的至少一个侧壁，在导电层中限定开口。 所述导电层包括与所述开口间隔开的端部，所述端部与所述基板的大致平坦的上表面形成锐角。 所述至少一个侧壁基本上垂直于所述基底的基本平坦的上表面。

公开(公告)号：US07325299B2

公开(公告)日：2008-02-05

申请号：US11619789

申请日：2007-01-04

申请人： Frank D. Egitto ,  Kevin T. Knadle ,  Andrew M. Seman

发明人： Frank D. Egitto ,  Kevin T. Knadle ,  Andrew M. Seman

IPC分类号： H05K3/02 ,  H05K3/10

CPC分类号： H05K3/06 ,  B32B15/08 ,  B32B15/20 ,  B32B27/04 ,  B32B27/06 ,  B32B27/30 ,  B32B27/38 ,  H01L21/32134 ,  H01L21/4846 ,  H01L21/76838 ,  H01L2924/0002 ,  H05K3/027 ,  H05K3/061 ,  H05K3/064 ,  H05K2203/0369 ,  H05K2203/1476 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49139 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T428/24322 ,  Y10T428/24802 ,  H01L2924/00

摘要： A method of making a circuitized substrate. A conductive layer having a substantially planar upper surface is formed on and in direct mechanical contact with an upper surface of a substrate. A portion of the conductive layer is removed to form an interim side wall in the conductive layer. A layer of patternable material is formed on the substantially planar upper surface and on the interim side wall. A portion of the layer of patternable material on the conductive layer is removed to expose the interim side wall. A portion of the substantially planar upper surface is removed to form a side wall in the layer of patternable material. Portions of the interim side wall in the conductive layer are removed to form a second side wall and a bottom wall defined by the upper surface of the substrate. The second side wall is substantially perpendicular to the bottom wall.

摘要翻译： 制造电路化基板的方法。 具有基本平坦的上表面的导电层形成在基板的上表面上并与基板的上表面直接机械接触。 去除导电层的一部分以在导电层中形成临时侧壁。 在基本平坦的上表面和临时侧壁上形成可图案化材料层。 去除导电层上图案化材料层的一部分以露出临时侧壁。 去除基本平坦的上表面的一部分以在可图案材料层中形成侧壁。 去除导电层中的临时侧壁的部分以形成由衬底的上表面限定的第二侧壁和底壁。 第二侧壁基本上垂直于底壁。

公开(公告)号：US09351408B2

公开(公告)日：2016-05-24

申请号：US12764997

申请日：2010-04-22

申请人： Voya Markovich ,  Timothy Antesberger ,  Frank D. Egitto ,  William Wilson ,  Rabindra N. Das

发明人： Voya Markovich ,  Timothy Antesberger ,  Frank D. Egitto ,  William Wilson ,  Rabindra N. Das

IPC分类号： H05K1/09 ,  H05K1/03 ,  H05K3/40

CPC分类号： H05K3/4069 ,  H05K3/4614 ,  H05K3/462 ,  H05K3/4623 ,  H05K2203/063

摘要： A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin. The substrate may also contain land grid array (LGA) packaging.

摘要翻译： 一种用于PCB或PWB板的衬底，其具有无芯堆积层和至少一个金属和至少一个介电层。 无芯堆积电介质层可由至少部分固化的热固性树脂和热塑性树脂组成。 衬底还可以包含焊盘阵列（LGA）封装。

公开(公告)号：US08536459B2

公开(公告)日：2013-09-17

申请号：US12764994

申请日：2010-04-22

申请人： Voya Markovich ,  Timothy Antesberger ,  Frank D. Egitto ,  William Wilson ,  Rabindra N. Das

发明人： Voya Markovich ,  Timothy Antesberger ,  Frank D. Egitto ,  William Wilson ,  Rabindra N. Das

IPC分类号： H05K1/03 ,  H05K1/02 ,  H05K1/09

CPC分类号： H05K3/4623 ,  H05K1/092 ,  H05K3/4053 ,  H05K3/4614 ,  H05K3/4691 ,  H05K2203/061

摘要： A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin. The substrate may also contain land grid array (LGA) packaging.

摘要翻译： 一种用于PCB或PWB板的衬底，其具有无芯堆积层和至少一个金属和至少一个介电层。 无芯堆积电介质层可由至少部分固化的热固性树脂和热塑性树脂组成。 衬底还可以包含焊盘阵列（LGA）封装。

公开(公告)号：US07875811B2

公开(公告)日：2011-01-25

申请号：US12010335

申请日：2008-01-24

申请人： David V. Caletka ,  Frank D. Egitto

发明人： David V. Caletka ,  Frank D. Egitto

IPC分类号： H01R12/04 ,  H05K1/11

CPC分类号： H05K1/0219 ,  H01R12/523 ,  H01R13/2414 ,  H05K1/113 ,  H05K3/4046 ,  H05K3/429 ,  H05K3/4614 ,  H05K2201/0959 ,  H05K2201/09809 ,  H05K2201/10303 ,  H05K2201/10378 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A high speed interposer which includes a substrate having alternatingly oriented dielectric and conductive layers which form a substrate, openings which extend from one opposing surface of the substrate to a second opposing surface, conductive members positioned within the openings and also extending from surface to surface (and beyond, in some embodiments), and a plurality of shielding members positioned substantially around the conductive members to provide shielding therefore during the passage of high frequency signals through the conductive members.

摘要翻译： 高速插入器，其包括具有交替取向的介电层和导电层的基板，其形成基板，从基板的一个相对表面延伸到第二相对表面的开口，定位在开口内并且还从表面延伸到表面的导电构件 并且在一些实施例中超越）以及基本上围绕导电构件定位的多个屏蔽构件，从而在高频信号通过导电构件期间提供屏蔽。

公开(公告)号：US07800916B2

公开(公告)日：2010-09-21

申请号：US11783306

申请日：2007-04-09

申请人： Kim J. Blackwell ,  Frank D. Egitto ,  John M. Lauffer ,  Voya R. Markovich

发明人： Kim J. Blackwell ,  Frank D. Egitto ,  John M. Lauffer ,  Voya R. Markovich

IPC分类号： H01R12/16

CPC分类号： H05K1/186 ,  H01L23/4985 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K3/4611 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/10515 ,  H05K2201/10681 ,  Y10T29/49126 ,  Y10T29/49151 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/0401

摘要： A circuitized substrate assembly comprised of at least two circuitized substrates each including a thin dielectric layer and a conductive layer with a plurality of conductive members as part thereof, the conductive members of each substrate being electrically coupled to the conductive sites of a semiconductor chip. A dielectric layer is positioned between both substrates and the substrates are bonded together, such that the chips are internally located within the assembly and oriented in a stacked orientation. A method of making such an assembly is also provided, as is an electrical assembly utilizing same and an information handling system adapted for having such an electrical assembly as part thereof.

摘要翻译： 电路化衬底组件由至少两个电路化衬底组成，每个衬底均包括薄介电层和具有多个导电构件作为其一部分的导电层，每个衬底的导电构件电耦合到半导体芯片的导电部位。 电介质层位于两个基板之间，并且基板接合在一起，使得芯片在内部位于组件内并且以堆叠取向定向。 还提供了制造这种组件的方法，以及使用其的电组件以及适于将这种电组件作为其一部分的信息处理系统。

公开(公告)号：US20080217050A1

公开(公告)日：2008-09-11

申请号：US11873435

申请日：2007-10-17

申请人： Frank D. Egitto ,  Donald S. Farquhar ,  Voya R. Markovich ,  Mark D. Poliks ,  Douglas O. Powell

发明人： Frank D. Egitto ,  Donald S. Farquhar ,  Voya R. Markovich ,  Mark D. Poliks ,  Douglas O. Powell

IPC分类号： H01R12/04 ,  B29C65/48

CPC分类号： H01L21/4853 ,  H01L23/3735 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/114 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/462 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4632 ,  H05K3/4641 ,  H05K3/4688 ,  H05K2201/0141 ,  H05K2201/0191 ,  H05K2201/068 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/10378 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T156/1092

摘要： A multi-layered interconnect structure and method of formation. In a first embodiment, first and second liquid crystal polymer (LCP) dielectric layers are directly bonded, respectively, to first and second opposing surface of a thermally conductive layer, with no extrinsic adhesive material bonding the thermally conductive layer with either the first or second LCP dielectric layer. In a second embodiment, first and second 2S1P substructures are directly bonded, respectively, to first and second opposing surfaces of a LCP dielectric joining layer, with no extrinsic adhesive material bonding the LCP dielectric joining layer with either the first or second 2S1P substructures.

摘要翻译： 多层互连结构和形成方法。 在第一实施例中，第一和第二液晶聚合物（LCP）电介质层分别直接接合到导热层的第一和第二相对表面，没有外在粘合材料将导热层与第一或第二液晶聚合物 LCP电介质层。 在第二实施例中，第一和第二2S1P子结构分别直接接合到LCP电介质接合层的第一和第二相对表面，没有外部粘合材料将LCP电介质接合层与第一或第二2S1P子结构结合。

公开(公告)号：US20080142258A1

公开(公告)日：2008-06-19

申请号：US12010335

申请日：2008-01-24

申请人： David V, Caletka ,  Frank D. Egitto

发明人： David V, Caletka ,  Frank D. Egitto

IPC分类号： H05K1/11

CPC分类号： H05K1/0219 ,  H01R12/523 ,  H01R13/2414 ,  H05K1/113 ,  H05K3/4046 ,  H05K3/429 ,  H05K3/4614 ,  H05K2201/0959 ,  H05K2201/09809 ,  H05K2201/10303 ,  H05K2201/10378 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A high speed interposer which includes a substrate having alternatingly oriented dielectric and conductive layers which form a substrate, openings which extend from one opposing surface of the substrate to a second opposing surface, conductive members positioned within the openings and also extending from surface to surface (and beyond, in some embodiments), and a plurality of shielding members positioned substantially around the conductive members to provide shielding therefore during the passage of high frequency signals through the conductive members.

摘要翻译： 高速插入器，其包括具有交替取向的介电层和导电层的基板，其形成基板，从基板的一个相对表面延伸到第二相对表面的开口，定位在开口内并且还从表面延伸到表面的导电构件 并且在一些实施例中超越）以及基本上围绕导电构件定位的多个屏蔽构件，从而在高频信号通过导电构件期间提供屏蔽。