METHOD AND APPARATUS TO REDUCE PIN VOIDS
    1.
    发明申请
    METHOD AND APPARATUS TO REDUCE PIN VOIDS 审中-公开
    减少PIN VOIDS的方法和装置

    公开(公告)号:US20090250824A1

    公开(公告)日:2009-10-08

    申请号:US12098311

    申请日:2008-04-04

    IPC分类号: H01L23/48 H01L21/00

    摘要: A semiconductor package comprises a substrate that utilizes one or more pins to form external interconnects. The pins are bonded to bonding pads on the substrate by solder. The pins may each has a pin head that may have a bonding surface, wherein the bonding surface may comprises a center portion and a side portion that is tapered away relative to the center portion. In some embodiments, the bonding surface may comprise a round shape. In some embodiments, a gas escape path may be provided by the shape of the bonding surface to increase pin pull strength and/or solder strength. The package may further comprise a surface finish that may comprise a palladium layer with a reduced thickness to reduce the amount of palladium based IMC precipitation into the solder.

    摘要翻译: 半导体封装包括利用一个或多个引脚形成外部互连的基板。 引脚通过焊料与基板上的焊盘接合。 销可以各自具有可以具有接合表面的销头,其中接合表面可以包括中心部分和相对于中心部分逐渐变细的侧部部分。 在一些实施例中,接合表面可以包括圆形。 在一些实施例中,可以通过接合表面的形状提供气体逸出路径,以增加引脚拉伸强度和/或焊接强度。 该封装还可以包括表面光洁度,其可以包括具有减小厚度的钯层,以减少基于钯的IMC沉淀到焊料中的量。