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    High electron mobility transistor
    2.
    发明授权
    High electron mobility transistor 失效
    高电子迁移率晶体管

    公开(公告)号：US5796127A

    公开(公告)日：1998-08-18

    申请号：US915791

    申请日：1997-08-21

    申请人： Norio Hayafuji ,  Yoshitsugu Yamamoto ,  Hirotaka Kizuki

    发明人： Norio Hayafuji ,  Yoshitsugu Yamamoto ,  Hirotaka Kizuki

    IPC分类号： H01L29/812 ,  H01L21/203 ,  H01L21/314 ,  H01L21/324 ,  H01L21/335 ,  H01L21/338 ,  H01L23/31 ,  H01L29/36 ,  H01L29/778 ,  H01L29/201 ,  H01L29/737

    CPC分类号： H01L29/66462 ,  H01L21/314 ,  H01L21/3245 ,  H01L23/3185 ,  H01L29/365 ,  H01L2924/0002

    摘要： A method of fabricating a semiconductor device includes forming a first mixed crystal semiconductor layer of AlAs and InAs; applying a solution containing a material easily combining with fluorine to the surface of the first mixed crystal semiconductor layer exposed to the atmosphere so that the material combines with fluorine that sticks to the surface of the first mixed crystal semiconductor layer; and annealing the first mixed crystal semiconductor layer in a vacuum. In this method, since the fluorine on the surface of the first mixed crystal semiconductor layer exposed to the atmosphere combines with the material included in the solution and is removed together with the material, a first mixed crystal semiconductor layer having no fluorine is produced. Therefore, unwanted infiltration of fluorine into the first mixed crystal semiconductor layer is avoided, resulting in a highly reliable semiconductor device with desired characteristics.

    摘要翻译： 制造半导体器件的方法包括：形成AlAs和InAs的第一混晶半导体层; 将含有容易与氟结合的材料的溶液施加到暴露于大气的第一混晶半导体层的表面，使得该材料与粘附在第一混晶半导体层表面的氟结合; 以及在真空中退火所述第一混晶半导体层。 在该方法中，由于暴露于大气中的第一混晶半导体层的表面上的氟与包含在溶液中的材料结合，与材料一起被除去，因此产生不含氟的第一混晶半导体层。 因此，避免了氟进入第一混晶半导体层的不必要的渗入，导致具有所需特性的高度可靠的半导体器件。

    Method of fabricating semiconductor device and semiconductor device fabricated thereby
    4.
    发明授权
    Method of fabricating semiconductor device and semiconductor device fabricated thereby 失效
    制造半导体器件的方法和由此制造的半导体器件

    公开(公告)号：US5682045A

    公开(公告)日：1997-10-28

    申请号：US525175

    申请日：1995-09-08

    申请人： Norio Hayafuji ,  Yoshitsugu Yamamoto

    发明人： Norio Hayafuji ,  Yoshitsugu Yamamoto

    IPC分类号： H01L29/812 ,  H01L21/285 ,  H01L21/324 ,  H01L21/335 ,  H01L21/338 ,  H01L29/778 ,  H01L31/0328

    CPC分类号： H01L29/66462 ,  H01L21/28587 ,  H01L21/3245

    摘要： An Si-doped AlInAs layer and an intrinsic AlInAs layer are successively grown on a semi-insulating InP substrate in a molecular beam epitaxy chamber. The sample is then heat-treated in a nitrogen ambient at 400.degree. C. for 18 minutes so that electrical characteristics of the sample are deteriorated because of the infiltration of fluorine into the Si-doped AlInAs layer. The sample is then placed in the molecular beam epitaxy chamber and reheat-treated in an ultra-high vacuum at 400.degree. C. for seven minutes and the fluorine is removed.

    摘要翻译： 在分子束外延室中的半绝缘InP衬底上依次生长Si掺杂的AlInAs层和本征AlInAs层。 然后将样品在氮气环境中在400℃下热处理18分钟，使得样品的电特性由于氟渗入Si掺杂的AlInAs层而劣化。 然后将样品置于分子束外延室中，并在400℃的超高真空中再加热处理7分钟，并除去氟。

    Field effect transistor
    5.
    发明授权
    Field effect transistor 失效
    场效应晶体管

    公开(公告)号：US5874753A

    公开(公告)日：1999-02-23

    申请号：US827059

    申请日：1997-03-26

    申请人： Norio Hayafuji ,  Yoshitsugu Yamamoto

    发明人： Norio Hayafuji ,  Yoshitsugu Yamamoto

    IPC分类号： H01L29/812 ,  H01L21/285 ,  H01L21/335 ,  H01L21/338 ,  H01L29/08 ,  H01L29/778 ,  H01L29/772

    CPC分类号： H01L29/66462 ,  H01L21/28587 ,  H01L29/0891 ,  H01L29/7783

    摘要： In a field effect transistor including active layers having a heterojunction structure with at least two different semiconductor materials, a layer for supplying electrons is disposed opposite a drain electrode, in contact with a region of the active layers including a dopant impurity producing n type conductivity. Therefore, degradation of the electrical characteristics caused by trapping of electrons in a drain ohmic contact layer due to fluorine diffusing into the semiconductor layers is suppressed by supplying electrons from the layer opposite the drain electrode, thereby improving reliability of the field effect transistor including the heterojunction structure.

    摘要翻译： 在包括具有至少两种不同半导体材料的异质结结构的有源层的场效应晶体管中，用于提供电子的层与漏极相对地设置，与包括产生n型导电性的掺杂剂杂质的有源层的区域相接触。 因此，通过从与漏电极相对的层提供电子来抑制由于氟扩散到半导体层而在漏极欧姆接触层中捕获电子引起的电特性的劣化，从而提高包括异质结的场效应晶体管的可靠性 结构体。

    Field effect transistor
    6.
    发明授权
    Field effect transistor 失效
    场效应晶体管

    公开(公告)号：US5811843A

    公开(公告)日：1998-09-22

    申请号：US805363

    申请日：1997-02-24

    申请人： Yoshitsugu Yamamoto ,  Norio Hayafuji

    发明人： Yoshitsugu Yamamoto ,  Norio Hayafuji

    IPC分类号： H01L29/812 ,  H01L21/338 ,  H01L29/778

    CPC分类号： H01L29/7783

    摘要： A field effect transistor includes a semi-insulating III-V compound semiconductor substrate; a channel layer disposed on the substrate; an n type electron supply layer disposed on the channel layer and comprising a mixed crystalline compound semiconductor layer including AlAs; an n type ohmic contact layer disposed on the electron supply layer; source and drain electrodes disposed on the ohmic contact layer; an opening in a region between the source and drain electrodes penetrating the ohmic contact layer; a gate electrode disposed in the opening and making a Schotty contact; and a surface protection film of a semiconductor material free of Al, In, and As, covering the opening except where the gate electrode is present. Fluorine is prevented from getting into the electron supply layer with no increase in transconductance or source resistance by providing a layer between the source and a channel, and between the gate and the channel.

    摘要翻译： 场效应晶体管包括半绝缘III-V化合物半导体衬底; 设置在所述基板上的沟道层; n型电子供给层，其设置在所述沟道层上，并且包括含有AlAs的混合晶体化合物半导体层; 设置在电子供给层上的n型欧姆接触层; 源极和漏极设置在欧姆接触层上; 在源极和漏极之间穿过欧姆接触层的区域中的开口; 设置在开口中并形成Schotty接触的栅电极; 以及不含有Al，In和As的半导体材料的表面保护膜，覆盖除了存在栅极之外的开口。 通过在源极和通道之间以及栅极和沟道之间提供一层，防止氟通过跨导或源极电阻的增加而进入电子供给层。

    Compound semiconductor structure including p-type and n-type regions doped with carbon
    8.
    发明授权
    Compound semiconductor structure including p-type and n-type regions doped with carbon 失效
    包括掺杂有碳的p型和n型区的化合物半导体结构

    公开(公告)号：US5315133A

    公开(公告)日：1994-05-24

    申请号：US928746

    申请日：1992-08-13

    申请人： Norio Hayafuji

    发明人： Norio Hayafuji

    IPC分类号： H01L21/205 ,  H01L21/331 ,  H01L29/205 ,  H01L29/73 ,  H01L29/737 ,  H01S5/00 ,  H01L33/00

    CPC分类号： H01L21/0262 ,  H01L21/02546 ,  H01L21/02576 ,  H01L21/02579 ,  Y10S438/925

    摘要： While depositing a III-V compound semiconductor layer from a vapor, carbon is added to group III and V elements to produce a p type conductivity region in the depositing semiconductor layer. Then, a small amount of n type dopant is added to the group III and V elements together with the carbon to produce an n type conductivity region in the depositing semiconductor layer. A sharp and precisely controlled doping profile is produced in the vicinity of a p-n junction, resulting in a semiconductor device having good initial performance and high reliability.

    摘要翻译： 在从蒸气中沉积III-V化合物半导体层的同时，将碳添加到III族和V族元素中，以在沉积半导体层中产生p型导电性区域。 然后，少量的n型掺杂剂与碳一起添加到III族和V族元素中，以在沉积半导体层中产生n型导电性区域。 在p-n结附近产生尖锐和精确控制的掺杂分布，导致半导体器件具有良好的初始性能和高可靠性。

    Method for forming a film by selective area MOCVD growth
    9.
    发明授权
    Method for forming a film by selective area MOCVD growth 失效
    通过选择性区域MOCVD生长形成膜的方法

    公开(公告)号：US5728215A

    公开(公告)日：1998-03-17

    申请号：US555707

    申请日：1995-11-14

    申请人： Takushi Itagaki ,  Masayoshi Takemi ,  Norio Hayafuji

    发明人： Takushi Itagaki ,  Masayoshi Takemi ,  Norio Hayafuji

    IPC分类号： H01L21/205 ,  C23C16/04 ,  H01S5/00 ,  C30B25/04

    CPC分类号： C23C16/042

    摘要： A method for forming a film by selective area growth by MDCVD technique includes forming a mask on a semiconductor substrate having a (100) plane, the mask having a mask opening to selectively growing a compound semiconductor layer, and a slit which is narrower than the mask opening in width and controls the growth rate of the compound semiconductor layer at the mask opening; and selectively growing the compound semiconductor layer at a growth rate which is on the mask in the mask opening and the slit.

    摘要翻译： 通过MDCVD技术通过选择性区域生长形成膜的方法包括在具有（100）面的半导体衬底上形成掩模，掩模具有掩模开口以选择性地生长化合物半导体层，以及狭缝比 掩模开口宽度并控制化合物半导体层在掩模开口处的生长速率; 并且以掩模开口和狭缝中的掩模上的生长速率选择性地生长化合物半导体层。

    Method of producing a semiconductor structure including a recrystallized film
    10.
    发明授权
    Method of producing a semiconductor structure including a recrystallized film 失效
    制造包括再结晶膜的半导体结构的方法

    公开(公告)号：US5467731A

    公开(公告)日：1995-11-21

    申请号：US322375

    申请日：1994-10-13

    申请人： Satoshi Arimoto ,  Norio Hayafuji ,  Mikio Deguchi ,  Satoshi Hamamoto

    发明人： Satoshi Arimoto ,  Norio Hayafuji ,  Mikio Deguchi ,  Satoshi Hamamoto

    IPC分类号： H01L21/208 ,  H01L21/20 ,  C30B13/20

    CPC分类号： H01L21/2022

    摘要： A method for producing a semiconductor structure including a semiconductor film formed on a semiconductor substrate body via an insulating film includes: laminating a first insulating film, a first semiconductor film, and a second insulating film on the semiconductor substrate successively; forming stripe-shaped second semiconductor films of predetermined width on the second insulating film arranged periodically at a predetermined interval and covering these second semiconductor films with a third insulating film; performing zone melting recrystallization of the first semiconductor film from one end of the substrate to the opposite end along the stripe direction of the stripe-shaped second semiconductor film; etching the third insulating film and portions of the second insulating film not sandwiched by the first and second semiconductor films; oxidizing portions of the second semiconductor film and the first semiconductor film exposed in the etching step and etching and removing the second insulating film remaining after the previous etching. Thus, a semiconductor substrate including a recrystallized semiconductor film having removed sub-grain-boundaries generated during the zone melting recrystallization, is obtained by fewer process steps than in the prior art.

    摘要翻译： 一种用于制造半导体结构的方法，该半导体结构包括通过绝缘膜形成在半导体衬底本体上的半导体膜，包括：依次在半导体衬底上层叠第一绝缘膜，第一半导体膜和第二绝缘膜; 在预定间隔周期性地布置的第二绝缘膜上形成预定宽度的条状第二半导体膜，并用第三绝缘膜覆盖这些第二半导体膜; 从所述基板的一端到所述条状的第二半导体膜的条带方向的相反端进行区域熔融再结晶的第一半导体膜; 蚀刻第三绝缘膜和未被第一和第二半导体膜夹持的第二绝缘膜的部分; 在蚀刻步骤中暴露的第二半导体膜和第一半导体膜的氧化部分，并蚀刻除去在先前蚀刻之后残留的第二绝缘膜。 因此，通过比现有技术更少的工艺步骤获得包括在区域熔融再结晶期间产生的去除亚晶界的再结晶半导体膜的半导体衬底。