专利检索 ap:("Ziptronix, Inc.") AND inv:"Paul M. Enquist" 第 1 页

1.

发明申请
3D IC METHOD AND DEVICE 审中-公开

公开(公告)号：US20170316971A1

公开(公告)日：2017-11-02

申请号：US15653329

申请日：2017-07-18

申请人： ZIPTRONIX, INC.

发明人： Paul M. Enquist , Gaius Gillman Fountain, JR. , Qin-Yi Tong

IPC分类号： H01L21/768 , H01L23/00 , H01L25/065 , H01L25/00 , H01L27/06 , H01L23/48

CPC分类号： H01L21/76838 , H01L21/76898 , H01L23/481 , H01L24/02 , H01L24/81 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L2224/0401 , H01L2224/81121 , H01L2224/81201 , H01L2224/8123 , H01L2224/81801 , H01L2224/81894 , H01L2224/81931 , H01L2224/83894 , H01L2224/9202 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/0102 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01049 , H01L2924/0105 , H01L2924/01055 , H01L2924/01059 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/10329 , H01L2924/12044 , H01L2924/14 , H01L2924/19043 , H01L2924/3025 , H01L2224/81

摘要： A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface.

2.

发明授权
Method for low temperature bonding and bonded structure 有权

公开(公告)号：US09391143B2

公开(公告)日：2016-07-12

申请号：US14957501

申请日：2015-12-02

申请人： ZIPTRONIX, INC.

发明人： Qin-Yi Tong , Gaius Gillman Fountain, Jr. , Paul M. Enquist

IPC分类号： H01L21/30 , H01L21/46 , H01L29/16 , H01L21/02 , H01L21/20 , H01L21/311 , H01L21/762 , H01L23/00 , H01L29/06 , H01L21/322 , H01L27/085

CPC分类号： H01L24/83 , H01L21/0206 , H01L21/2007 , H01L21/31105 , H01L21/31116 , H01L21/322 , H01L21/76251 , H01L24/26 , H01L24/75 , H01L25/0657 , H01L25/50 , H01L27/085 , H01L29/06 , H01L29/16 , H01L2224/8301 , H01L2224/8303 , H01L2224/83031 , H01L2224/8309 , H01L2224/83099 , H01L2224/8319 , H01L2224/8385 , H01L2224/83894 , H01L2224/83896 , H01L2224/83948 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01018 , H01L2924/0102 , H01L2924/01023 , H01L2924/01033 , H01L2924/01039 , H01L2924/0106 , H01L2924/01061 , H01L2924/01072 , H01L2924/01074 , H01L2924/01075 , H01L2924/01084 , H01L2924/01093 , H01L2924/0132 , H01L2924/05442 , H01L2924/07802 , H01L2924/10253 , H01L2924/10329 , H01L2924/14 , Y10S148/012 , Y10S438/974 , Y10T156/10 , Y10T156/1043 , H01L2924/01014 , H01L2924/01015 , H01L2924/01049 , H01L2924/01031 , H01L2924/3512 , H01L2924/00

摘要： A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.

3.

发明申请
3D IC METHOD AND DEVICE 有权

公开(公告)号：US20130178062A1

公开(公告)日：2013-07-11

申请号：US13783553

申请日：2013-03-04

申请人： Ziptronix, Inc.

发明人： Paul M. Enquist , Gaius Gillman Fountain, JR. , Qin-Yi Tong

IPC分类号： H01L21/768

CPC分类号： H01L21/76838 , H01L21/76898 , H01L23/481 , H01L24/02 , H01L24/81 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L2224/0401 , H01L2224/81121 , H01L2224/81201 , H01L2224/8123 , H01L2224/81801 , H01L2224/81894 , H01L2224/81931 , H01L2224/83894 , H01L2224/9202 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/0102 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01049 , H01L2924/0105 , H01L2924/01055 , H01L2924/01059 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/10329 , H01L2924/12044 , H01L2924/14 , H01L2924/19043 , H01L2924/3025 , H01L2224/81

摘要： A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface. Alternatively, first and/or second contact structures are not exposed at bonding, and a via is etched and filled after bonding to electrically interconnect first and second contact structures and provide electrical access to interconnected first and second contact structure to a surface. Also, a device may be formed in a first substrate, the device being disposed in a device region of the first substrate and having a first contact structure. A via may be etched, or etched and filled, through the device region and into the first substrate before bonding and the first substrate thinned to expose the via, or filled via after bonding.

4.

发明申请
THREE DIMENSIONAL DEVICE INTEGRATION METHOD AND INTEGRATED DEVICE 审中-公开

公开(公告)号：US20170170132A1

公开(公告)日：2017-06-15

申请号：US15385545

申请日：2016-12-20

申请人： ZIPTRONIX, INC.

发明人： Paul M. Enquist , Gaius Gillman Fountain, JR.

IPC分类号： H01L23/00 , H01L25/00 , H01L25/065

CPC分类号： H01L24/08 , H01L21/187 , H01L21/2007 , H01L21/6835 , H01L21/76251 , H01L21/76898 , H01L21/8221 , H01L23/13 , H01L23/36 , H01L23/481 , H01L23/5384 , H01L23/5385 , H01L23/5389 , H01L23/552 , H01L24/24 , H01L24/26 , H01L24/27 , H01L24/30 , H01L24/48 , H01L24/80 , H01L24/82 , H01L24/83 , H01L24/94 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/16 , H01L25/167 , H01L25/18 , H01L25/50 , H01L27/0688 , H01L27/14634 , H01L2221/6835 , H01L2221/68359 , H01L2221/68363 , H01L2223/6677 , H01L2224/0807 , H01L2224/08123 , H01L2224/1134 , H01L2224/16 , H01L2224/24011 , H01L2224/24225 , H01L2224/24226 , H01L2224/24227 , H01L2224/3005 , H01L2224/30104 , H01L2224/305 , H01L2224/48091 , H01L2224/48101 , H01L2224/48227 , H01L2224/48247 , H01L2224/80896 , H01L2224/81894 , H01L2224/8303 , H01L2224/83092 , H01L2224/83099 , H01L2224/8319 , H01L2224/83193 , H01L2224/83345 , H01L2224/83359 , H01L2224/8385 , H01L2224/83894 , H01L2224/83896 , H01L2224/83912 , H01L2224/83948 , H01L2224/9202 , H01L2224/9212 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2225/06555 , H01L2225/06589 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01057 , H01L2924/01074 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/05442 , H01L2924/07802 , H01L2924/10253 , H01L2924/10329 , H01L2924/1305 , H01L2924/13062 , H01L2924/13063 , H01L2924/13064 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/15153 , H01L2924/15165 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/351 , Y10S148/012 , Y10S438/977 , H01L2224/13099 , H01L2924/01049 , H01L2924/01031 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/8203 , H01L2224/821 , H01L2224/80001 , H01L2224/82

摘要： A method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed.

5.

发明申请
THREE DIMENSIONAL DEVICE INTEGRATION METHOD AND INTEGRATED DEVICE 有权
标题翻译：三维设备集成方法和集成设备

公开(公告)号：US20160190093A1

公开(公告)日：2016-06-30

申请号：US15064467

申请日：2016-03-08

申请人： ZIPTRONIX, INC.

发明人： Paul M. Enquist , Gaius Gillman Fountain, JR.

IPC分类号： H01L23/00 , H01L25/065 , H01L25/00 , H01L23/538

CPC分类号： H01L24/08 , H01L21/187 , H01L21/2007 , H01L21/6835 , H01L21/76251 , H01L21/76898 , H01L21/8221 , H01L23/13 , H01L23/36 , H01L23/481 , H01L23/5384 , H01L23/5385 , H01L23/5389 , H01L23/552 , H01L24/24 , H01L24/26 , H01L24/27 , H01L24/30 , H01L24/48 , H01L24/80 , H01L24/82 , H01L24/83 , H01L24/94 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/16 , H01L25/167 , H01L25/18 , H01L25/50 , H01L27/0688 , H01L27/14634 , H01L2221/6835 , H01L2221/68359 , H01L2221/68363 , H01L2223/6677 , H01L2224/0807 , H01L2224/08123 , H01L2224/1134 , H01L2224/16 , H01L2224/24011 , H01L2224/24225 , H01L2224/24226 , H01L2224/24227 , H01L2224/3005 , H01L2224/30104 , H01L2224/305 , H01L2224/48091 , H01L2224/48101 , H01L2224/48227 , H01L2224/48247 , H01L2224/80896 , H01L2224/81894 , H01L2224/8303 , H01L2224/83092 , H01L2224/83099 , H01L2224/8319 , H01L2224/83193 , H01L2224/83345 , H01L2224/83359 , H01L2224/8385 , H01L2224/83894 , H01L2224/83896 , H01L2224/83912 , H01L2224/83948 , H01L2224/9202 , H01L2224/9212 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2225/06555 , H01L2225/06589 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01057 , H01L2924/01074 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/05442 , H01L2924/07802 , H01L2924/10253 , H01L2924/10329 , H01L2924/1305 , H01L2924/13062 , H01L2924/13063 , H01L2924/13064 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/15153 , H01L2924/15165 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/351 , Y10S148/012 , Y10S438/977 , H01L2224/13099 , H01L2924/01049 , H01L2924/01031 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/8203 , H01L2224/821 , H01L2224/80001 , H01L2224/82

摘要： A method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed.

摘要翻译： 一种方法可以包括将具有衬底的半导体器件直接接合到元件的步骤; 以及去除所述衬底的一部分以在结合之后露出所述半导体器件的剩余部分。元件可以包括用于热扩散，阻抗匹配或RF隔离的衬底之一，天线以及由无源元件组成的匹配网络。第二热扩散基板可以结合到半导体器件的其余部分。互连可以通过第一或第二基底进行。该方法还可以包括将多个半导体器件接合到元件，并且元件可以具有设置半导体器件的凹部。

6.

发明申请
METHOD FOR LOW TEMPERATURE BONDING AND BONDED STRUCTURE 有权

公开(公告)号：US20160086913A1

公开(公告)日：2016-03-24

申请号：US14957501

申请日：2015-12-02

申请人： ZIPTRONIX, INC.

发明人： Qin-Yi Tong , Gaius Gillman Fountain, JR. , Paul M. Enquist

IPC分类号： H01L23/00

CPC分类号： H01L24/83 , H01L21/0206 , H01L21/2007 , H01L21/31105 , H01L21/31116 , H01L21/322 , H01L21/76251 , H01L24/26 , H01L24/75 , H01L25/0657 , H01L25/50 , H01L27/085 , H01L29/06 , H01L29/16 , H01L2224/8301 , H01L2224/8303 , H01L2224/83031 , H01L2224/8309 , H01L2224/83099 , H01L2224/8319 , H01L2224/8385 , H01L2224/83894 , H01L2224/83896 , H01L2224/83948 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01018 , H01L2924/0102 , H01L2924/01023 , H01L2924/01033 , H01L2924/01039 , H01L2924/0106 , H01L2924/01061 , H01L2924/01072 , H01L2924/01074 , H01L2924/01075 , H01L2924/01084 , H01L2924/01093 , H01L2924/0132 , H01L2924/05442 , H01L2924/07802 , H01L2924/10253 , H01L2924/10329 , H01L2924/14 , Y10S148/012 , Y10S438/974 , Y10T156/10 , Y10T156/1043 , H01L2924/01014 , H01L2924/01015 , H01L2924/01049 , H01L2924/01031 , H01L2924/3512 , H01L2924/00

摘要： A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.

7.

发明申请
METHOD FOR LOW TEMPERATURE BONDING AND BONDED STRUCTURE 审中-公开
标题翻译：低温结合和粘结结构的方法

公开(公告)号：US20140203407A1

公开(公告)日：2014-07-24

申请号：US14197056

申请日：2014-03-04

申请人： Ziptronix, Inc.

发明人： Qin-Yi TONG , Gaius Gillman Fountain, JR. , Paul M. Enquist

IPC分类号： H01L29/06

CPC分类号： H01L24/83 , H01L21/0206 , H01L21/2007 , H01L21/31105 , H01L21/31116 , H01L21/322 , H01L21/76251 , H01L24/26 , H01L24/75 , H01L25/0657 , H01L25/50 , H01L27/085 , H01L29/06 , H01L29/16 , H01L2224/8301 , H01L2224/8303 , H01L2224/83031 , H01L2224/8309 , H01L2224/83099 , H01L2224/8319 , H01L2224/8385 , H01L2224/83894 , H01L2224/83896 , H01L2224/83948 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01018 , H01L2924/0102 , H01L2924/01023 , H01L2924/01033 , H01L2924/01039 , H01L2924/0106 , H01L2924/01061 , H01L2924/01072 , H01L2924/01074 , H01L2924/01075 , H01L2924/01084 , H01L2924/01093 , H01L2924/0132 , H01L2924/05442 , H01L2924/07802 , H01L2924/10253 , H01L2924/10329 , H01L2924/14 , Y10S148/012 , Y10S438/974 , Y10T156/10 , Y10T156/1043 , H01L2924/01014 , H01L2924/01015 , H01L2924/01049 , H01L2924/01031 , H01L2924/3512 , H01L2924/00

摘要： A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.

摘要翻译： 在低温或室温下接合的方法包括通过清洗或蚀刻进行表面清洁和活化的步骤。该方法还可以包括除去界面聚合的副产物以防止反向聚合反应，以允许诸如硅，氮化硅和SiO 2的材料的室温化学键合。要结合的表面被抛光到高度的平滑度和平坦度。 VSE可以使用反应离子蚀刻或湿蚀刻来稍微蚀刻被结合的表面。表面粗糙度和平面度不会降低，并且可以通过VSE工艺增强。蚀刻的表面可以在诸如氢氧化铵或氟化铵的溶液中冲洗以促进在表面上形成所需的粘结物质。

8.

发明申请
INCREASED CONTACT ALIGNMENT TOLERANCE FOR DIRECT BONDING 有权

公开(公告)号：US20170179029A1

公开(公告)日：2017-06-22

申请号：US15379942

申请日：2016-12-15

申请人： ZIPTRONIX, INC.

发明人： Paul M. Enquist , Gaius Gillman Fountain, JR. , Javier A. DeLaCruz

IPC分类号： H01L23/528 , H01L21/768 , H01L23/522

CPC分类号： H01L23/5283 , H01L21/76838 , H01L23/5226 , H01L24/02 , H01L25/0657 , H01L25/50 , H01L2224/16145 , H01L2224/80 , H01L2225/06513 , H01L2225/06555 , H01L2225/06593

摘要： A bonded device structure including a first substrate having a first set of conductive contact structures, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the contact structures on the first substrate, a second substrate having a second set of conductive contact structures, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the contact structures on the second substrate, and a contact-bonded interface between the first and second set of contact structures formed by contact bonding of the first non-metallic region to the second non-metallic region. The contact structures include elongated contact features, such as individual lines or lines connected in a grid, that are non-parallel on the two substrates, making contact at intersections. Alignment tolerances are thus improved while minimizing dishing and parasitic capacitance.