公开(公告)号：WO2018063302A1

公开(公告)日：2018-04-05

申请号：PCT/US2016/054710

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： GLASS, Glenn A. ,  JAMBUNATHAN, Karthik ,  MURTHY, Anand S. ,  MOHAPATRA, Chandra S. ,  MORROW, Patrick ,  KOBRINSKY, Mauro J.

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/41766 ,  H01L21/76898 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/845 ,  H01L23/481 ,  H01L23/485 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0669 ,  H01L29/41791 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/7851

Abstract: Techniques are disclosed for backside source/drain (S/D) replacement for semiconductor devices with metallization on both sides (MOBS). The techniques described herein provide methods to recover or otherwise facilitate low contact resistance, thereby reducing or eliminating parasitic external resistance that degrades transistor performance. In some cases, the techniques include forming sacrificial S/D material and a seed layer during frontside processing of a device layer including one or more transistor devices. The device layer can then be inverted and bonded to a host wafer. A backside reveal of the device layer can then be performed via grinding, etching, and/or CMP processes. The sacrificial S/D material can then be removed through backside S/D contact trenches using the seed layer as an etch stop, followed by the formation of relatively highly doped final S/D material grown from the seed layer, to provide enhanced ohmic contact properties. Other embodiments may be described and/or disclosed.

Abstract translation: 公开了用于具有两面金属化（MOBS）的半导体器件的背面源极/漏极（S / D）替换的技术。 本文描述的技术提供了恢复或以其他方式促进低接触电阻的方法，由此减少或消除使晶体管性能劣化的寄生外部电阻。 在一些情况下，这些技术包括在包括一个或多个晶体管器件的器件层的正面处理期间形成牺牲S / D材料和籽晶层。 器件层然后可以倒置并结合到主晶圆。 然后可以通过研磨，蚀刻和/或CMP工艺来执行器件层的背面显示。 然后可以使用晶种层作为蚀刻停止层通过背侧S / D接触沟槽去除牺牲S / D材料，接着形成从晶种层生长的相对高度掺杂的最终S / D材料，以提供增强的欧姆接触 属性。 其他实施例可以被描述和/或公开。

公开(公告)号：WO2018004645A1

公开(公告)日：2018-01-04

申请号：PCT/US2016/040668

申请日：2016-07-01

Applicant: INTEL CORPORATION

Inventor： LEE, Chen-Guan ,  HAFEZ, Walid M. ,  PARK, Joodong ,  CASSIDY-COMFORT, Everett S. ,  LIU, En-Shao

IPC: H01L21/768 ,  H01L21/8234

CPC classification number: H01L27/0629 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5228 ,  H01L27/0886 ,  H01L28/20 ,  H01L29/41791

Abstract: An embodiment includes an apparatus comprising: a fin based field effect transistor (FinFET) comprising a source, a drain, and a gate; a contact coupled to at least one of the source, the drain, and the gate; a thin film resistor (TFR); a first via coupled to the contact and a second via coupled to the TFR; and a bottom metallization (M) layer and additional M layers above the bottom M layer; wherein the TFR and the first and second vias are all below the bottom M layer. Other embodiments are described herein.

Abstract translation: 一个实施例包括一种装置，该装置包括：基于鳍的场效应晶体管（FinFET），其包括源极，漏极和栅极; 耦合到所述源极，所述漏极和所述栅极中的至少一个的接触; 薄膜电阻（TFR）; 耦合到所述触点的第一通孔和耦合到所述TFR的第二通孔; 和底部金属化（M）层以及底部M层上方的附加M层; 其中所述TFR和所述第一和第二通孔全部在所述底部M层下方。 这里描述了其他实施例。

公开(公告)号：WO2017122105A1

公开(公告)日：2017-07-20

申请号：PCT/IB2017/050050

申请日：2017-01-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  IBM (CHINA) INVESTMENT COMPANY LIMITED

Inventor： BAO, Ruqiang ,  KRISHNAN, Siddarth ,  KWON, Unoh ,  NARAYANAN, Vijay

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/66 ,  H01L29/49 ,  H01L27/092

CPC classification number: H01L27/0924 ,  H01L21/28088 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, depositing a scavenging layer on the first nitride layer, forming a capping layer over the scavenging layer, removing portions of the capping layer and the scavenging layer to expose a portion of the first nitride layer in a n-type field effect transistor (nFET) region of the gate stack, forming a first gate metal layer over the first nitride layer and the capping layer, depositing a second nitride layer on the first gate metal layer, and depositing a gate electrode material on the second nitride layer.

Abstract translation: 一种用于制造半导体器件的栅极叠层的方法包括：在器件的沟道区上形成第一介电层;在第一介电层上形成第一氮化物层;在第一介电层上沉积清除层 第一氮化物层;在所述清除层之上形成覆盖层;去除所述覆盖层和所述清除层的部分，以暴露所述栅极堆叠的n型场效应晶体管（nFET）区域中的所述第一氮化物层的一部分;形成 在第一氮化物层和覆盖层之上的第一栅极金属层，在第一栅极金属层上沉积第二氮化物层，以及在第二氮化物层上沉积栅电极材料。

公开(公告)号：WO2017052562A1

公开(公告)日：2017-03-30

申请号：PCT/US2015/052033

申请日：2015-09-24

Applicant: INTEL CORPORATION ,  MORROW, Patrick ,  KOBRINSKY, Mauro J. ,  JUN, Kimin ,  SON, Il-Seok ,  FISCHER, Paul B.

Inventor： MORROW, Patrick ,  KOBRINSKY, Mauro J. ,  JUN, Kimin ,  SON, Il-Seok ,  FISCHER, Paul B.

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/41791 ,  H01L21/845 ,  H01L27/1211

Abstract: Methods and structures formed thereby are described, of forming self-aligned contact structures for microelectronic devices. An embodiment includes forming a trench in a source/drain region of a transistor device disposed in a device layer, wherein the device layer is on a substrate, forming a fill material in the trench, forming a source/drain material on the fill material, forming a first source/drain contact on a first side of the source/drain material, and then forming a second source drain contact on a second side of the source/drain material.

Abstract translation: 描述了由此形成的方法和结构，用于形成用于微电子器件的自对准接触结构。 实施例包括在设置在器件层中的晶体管器件的源极/漏极区域中形成沟槽，其中器件层位于衬底上，在沟槽中形成填充材料，在填充材料上形成源极/漏极材料， 在源极/漏极材料的第一侧上形成第一源极/漏极接触，然后在源极/漏极材料的第二侧上形成第二源极漏极接触。

公开(公告)号：WO2016191407A1

公开(公告)日：2016-12-01

申请号：PCT/US2016/033876

申请日：2016-05-24

Applicant: QUALCOMM INCORPORATED

Inventor： BAO, Junjing ,  YANG, Haining ,  LIU, Yanxiang ,  XU, Jeffrey Junhao

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/495 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/288 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/32134 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: A sacrificial cap is grown on an upper surface of a conductor. A dielectric spacer is against a side of the conductor. An upper dielectric side spacer is formed on a sidewall of the sacrificial cap. The sacrificial cap is selectively etched, leaving a cap recess, and the upper dielectric side spacer facing the cap recess. Silicon nitride is filled in the cap recess, to form a center cap and a protective cap having center cap and the upper dielectric spacer.

Abstract translation: 在导体的上表面上生长牺牲帽。 电介质隔离物抵靠导体的一侧。 在绝缘帽的侧壁上形成上绝缘侧绝缘体。 牺牲帽被选择性地蚀刻，留下盖子凹槽，并且上电介质侧隔离物面向盖凹槽。 氮化硅填充在盖凹部中，以形成中心帽和具有中心帽和上部电介质间隔物的保护帽。

公开(公告)号：WO2015032274A9

公开(公告)日：2016-03-24

申请号：PCT/CN2014084756

申请日：2014-08-20

Applicant: IBM ,  IBM CHINA CO LTD

Inventor： NACZAS SEBASTIAN ,  PARUCHURI VAMSI ,  REZNICEK ALEXANDER ,  SCHEPIS DOMINIC J

IPC: H01L29/78

CPC classification number: H01L23/535 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A low resistance contact to a finFET source/drain can be achieved by forming a defect free surface on which to form such contact. The fins of a finFET can be exposed to epitaxial growth conditions to increase the bulk of semiconductive material in the source/drain. Facing growth fronts can merge or can form unmerged facets. A dielectric material can fill voids within the source drain region. A trench spaced from the finFET gate can expose the top portion of faceted epitaxial growth on fins within said trench, such top portions separated by a smooth dielectric surface. A silicon layer selectively formed on the top portions exposed within the trench can be converted to a semiconductor-metal layer, connecting such contact with individual fins in the source drain region.

Abstract translation: 可以通过形成在其上形成这种接触的无缺陷表面来实现对finFET源极/漏极的低电阻接触。 finFET的翅片可以暴露于外延生长条件以增加源极/漏极中的半导体材料的体积。 面对增长的前沿可以合并或形成未成熟的方面。 电介质材料可以填充源极漏极区域内的空隙。 与finFET栅极隔开的沟槽可以暴露在所述沟槽内的鳍片上的刻面外延生长的顶部，这些顶部由光滑电介质表面分开。 选择性地形成在暴露在沟槽内的顶部上的硅层可以转化为半导体金属层，将这种接触与源极漏极区域中的各个鳍连接。

公开(公告)号：WO2016032528A1

公开(公告)日：2016-03-03

申请号：PCT/US2014/053535

申请日：2014-08-29

Applicant: INTEL CORPORATION

Inventor： STEIGERWALD, Joseph M. ,  LINDERT, Nick

IPC: H01L23/48 ,  H01L21/60

CPC classification number: H01L21/823475 ,  H01L21/304 ,  H01L21/3085 ,  H01L21/823431 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: Embodiments of the present disclosure describe techniques for filling a high aspect ratio, narrow structure with multiple metal layers and associated configurations. In one embodiment, an apparatus includes a transistor structure comprising a semiconductor material, a dielectric material having a recess defined over the transistor structure, the recess having a height in a first direction, an electrode terminal disposed in the recess and coupled with the transistor structure, wherein a first portion of the electrode terminal comprises a first metal in direct contact with the transistor structure and a second portion of the electrode terminal comprises a second metal disposed on the first portion and wherein an interface between the first portion and the second portion is planar and extends across the recess in a second direction that is substantially perpendicular to the first direction. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了用于填充高纵横比，具有多个金属层的窄结构和相关配置的技术。 在一个实施例中，一种装置包括晶体管结构，该晶体管结构包括半导体材料，介电材料，其具有限定在该晶体管结构上的凹部，该凹部具有在第一方向上的高度;电极端子，设置在该凹槽中并与该晶体管结构 ，其中所述电极端子的第一部分包括与所述晶体管结构直接接触的第一金属，并且所述电极端子的第二部分包括设置在所述第一部分上的第二金属，并且其中所述第一部分和所述第二部分之间的界面是 并且在基本上垂直于第一方向的第二方向上延伸穿过凹部。 可以描述和/或要求保护其他实施例。

公开(公告)号：WO2015149705A1

公开(公告)日：2015-10-08

申请号：PCT/CN2015/075721

申请日：2015-04-01

Applicant: 唐棕

Inventor： 李迪

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/06

CPC classification number: H01L29/785 ,  H01L21/30604 ,  H01L21/30625 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7853 ,  H01L29/7854 ,  H01L2029/7858

Abstract: 本发明提供一种能够有效控制源漏区之间漏电流、提高栅极控制能力的鳍型半导体结构。所述鳍型半导体结构包括：具有下部衬底和鳍片部的鳍型衬底，形成在鳍片部上的源区和漏区，形成在所述源漏区之间横跨在鳍片部上的栅极结构，形成在所述鳍片部两侧且位于栅极结构下方的浅沟道隔离，以及形成在所述鳍片部中的隔离区。隔离区可以基本位于源区下方；和/或基本位于漏区下方；和/或基本位于栅极结构下方。本发明还提出了一种上述半导体结构的成型方法。

公开(公告)号：WO2015094309A1

公开(公告)日：2015-06-25

申请号：PCT/US2013/076694

申请日：2013-12-19

Applicant: INTEL CORPORATION ,  LEIB, Jeffrey S. ,  TROEGER, Ralph T. ,  BERGSTROM, Daniel B.

Inventor： LEIB, Jeffrey S. ,  TROEGER, Ralph T. ,  BERGSTROM, Daniel B.

IPC: H01L21/28

CPC classification number: H01L21/76895 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/76865 ,  H01L21/76883 ,  H01L23/528 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Techniques and methods related to forming a wrap-around contact on a semiconductor device, and apparatus, system, and mobile platform incorporating such semiconductor devices.

Abstract translation: 涉及在半导体器件上形成环绕接触的技术和方法，以及包括这种半导体器件的装置，系统和移动平台。

公开(公告)号：WO2015023877A1

公开(公告)日：2015-02-19

申请号：PCT/US2014/051124

申请日：2014-08-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： HE, Hong ,  TSENG, Chiahsun ,  YEH, Chun-Chen ,  YIN, Yunpeng

IPC: H01L21/302

CPC classification number: H01L21/31111 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor devices and sidewall image transfer methods with a spin on hardmask. Methods for forming fins include forming (1304) a trench through a stack of layers that includes a top and bottom insulator layer, and a layer to be patterned on a substrate; isotropically etching (1306) the top and bottom insulator layers; forming (1308) a hardmask material in the trench to the level of the bottom insulator layer; isotropically etching (1310) the top insulator layer; and etching (1312) the bottom insulator layer and the layer to be patterned down to the substrate to form fins from the layer to be patterned.

Abstract translation: 半导体器件和侧壁图像传输方法，在硬掩模上旋转。 用于形成翅片的方法包括：通过包括顶部和底部绝缘体层的层叠层形成（1304）沟槽，以及在衬底上形成图案化层; 各向同性地蚀刻（1306）顶部和底部绝缘体层; 在所述沟槽中形成（1308）硬掩模材料至所述底部绝缘体层的水平面; 各向同性蚀刻（1310）顶层绝缘体层; 并将底部绝缘体层和待图案化的层（1312）蚀刻到衬底上以从待图案化的层形成翅片。