公开(公告)号：WO2006044804A2

公开(公告)日：2006-04-27

申请号：PCT/US2005037258

申请日：2005-10-17

Applicant: CHIPPAC INC ,  HA JONGWOO ,  JUNG TAEBOK

Inventor： HA JONGWOO ,  JUNG TAEBOK

IPC: H01L21/50 ,  H01L23/495

CPC classification number: H01L24/32 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/4951 ,  H01L23/49548 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32188 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/4826 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01052 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A multichip package has a leadframe including peripheral leads arranged about a centrally situated die paddle. A first ("upper") die is attached to a first ("top") side of the leadframe die paddle, which can be generally flat. The second ("bottom") side of the leadframe is partially cut away (such as by partial etching), so that an outer part of the die paddle is thinner, and so that an inner part of the leads is thinner. These partially cutaway portions in the second ('bottom") side of the leadframe provide a cavity, in which a second ("lower") die is attached active side upward. The lower die may have bond pads situated near the center of the active surface, and electrical interconnection of the lower die may be made by wire bonds running through the gap between the die paddle and the leads; or, the lower die may be attached, and electrically interconnected, by flip chip interconnect to the die attach side of the cavity in the leadframe. Also, multipackage modules include at least one such multichip leadframe package.

Abstract translation: 多芯片封装具有引线框架，该引线框架包括围绕中心定位的芯片的周边引线。 第一（“上”）模具附接到引线框模片的第一（“顶部”）侧，其可以是大致平坦的。 引线框架的第二（“底”）侧被部分切除（例如通过部分蚀刻），使得芯片的外部部分更薄，并且引线的内部部分更薄。 引线框架的第二（“底”）侧的这些部分切除的部分提供了一个空腔，其中第二（“下”）管芯的主动侧面向上附接，下模可以具有位于活动中心附近的接合垫 下模的表面和电互连可以通过穿过芯片和导线之间的间隙的线接合来制成;或者，下模可以通过倒装芯片互连连接到电连接到芯片连接侧 引线框架中的空腔。此外，多包装模块包括至少一个这样的多芯片引线框架封装。

公开(公告)号：WO2005022591A2

公开(公告)日：2005-03-10

申请号：PCT/US2004/026790

申请日：2004-08-18

Applicant: ADVANCED INTERCONNECT TECHNOLOGIES LIMITED ,  ISLAM, Shafidul ,  SAN ANTONIO, Romarico, Santos

Inventor： ISLAM, Shafidul ,  SAN ANTONIO, Romarico, Santos

IPC: H01L

CPC classification number: H01L21/4832 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L25/105 ,  H01L2221/68377 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32257 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/84439 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/85 ,  H01L2924/0665 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099

Abstract: A semiconductor device package includes an electrically conductive lead frame having a plurality of posts disposed at a perimeter of the package. Each of the posts has a first contact surface disposed at the first package face and a second contact surface disposed at the second package face. The lead frame also includes a plurality of post extensions disposed at the second package face. Each of the post extensions includes a bond site formed on a surface of the post extension opposite the second package face. At least one I/O pads on the semiconductor device is electrically connected to the post extension at the bond site using wirebonding, tape automated bonding, or flip-chip methods. The package can be assembled use a lead frame having pre-formed leads, with or without taping, or it can employ the use of partially etched lead frames. A stack of the semiconductor device packages may be formed.

Abstract translation: 半导体器件封装包括导电引线框架，该导电引线框架具有设置在封装的周边处的多个柱。 每个柱具有设置在第一包装面处的第一接触表面和设置在第二包装面处的第二接触表面。 引线框架还包括设置在第二包装面处的多个支柱延伸部。 每个柱延伸部包括形成在柱延伸部的与第二包装面相对的表面上的结合部位。 半导体器件上的至少一个I / O焊盘使用引线键合，带式自动键合或倒装芯片方法在键合位置处电连接到柱延伸部分。 封装可以使用具有预成型引线的引线框架进行组装，有或没有胶带，或者可以使用部分蚀刻的引线框架。 可以形成一堆半导体器件封装。

公开(公告)号：WO00068996A1

公开(公告)日：2000-11-16

申请号：PCT/US1999/025015

申请日：1999-10-26

IPC: H01L21/98 ,  H01L25/10 ,  H01L25/11 ,  H01L25/18 ,  H05K1/14 ,  H05K1/18 ,  H05K3/34

CPC classification number: H01L25/50 ,  H01L25/105 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/14 ,  H01L2924/1627 ,  H05K1/141 ,  H05K1/182 ,  H05K3/3442 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10689 ,  H05K2203/0173 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Packaged surface mount (SMT) chips having matched top contacts and bottom contacts are stacked. Chip features are selected to provide the desired connectivity between chip layers with a greater ease of manufacture. In one embodiment, additional spacing and routing layers are optionally provided between layers. In another, chips are differentiated by optionally providing different conductor and/or nonvolatile cell configurations. In yet another, a minority of a substrate's contacts are configured for aligning with a dielectric region of a spacing layer or substrate to create very low capacitance signal paths between stacked chips.

Abstract translation: 堆叠具有匹配的顶部触点和底部触点的封装表面贴装（SMT）芯片。 选择芯片特征以在芯片层之间提供期望的连接性，并且更容易制造。 在一个实施例中，可选地在层间提供附加间隔和布线层。 另一方面，通过可选地提供不同的导体和/或非易失性电池配置来区分芯片。 另一方面，少数衬底的触点被配置为与间隔层或衬底的电介质区域对准，以在堆叠的芯片之间产生非常低的电容信号路径。

公开(公告)号：WO00065652A1

公开(公告)日：2000-11-02

申请号：PCT/US2000/004988

申请日：2000-02-25

IPC: H01L23/538 ,  H01L25/10 ,  H05K1/02 ,  H05K1/14 ,  H05K1/18 ,  H05K3/34 ,  H01L23/02 ,  H01L23/043 ,  H01L23/10 ,  H01L23/15

CPC classification number: H01L23/5385 ,  H01L25/105 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/0002 ,  H05K1/0231 ,  H05K1/141 ,  H05K1/181 ,  H05K3/3421 ,  H05K2201/10325 ,  H05K2201/10522 ,  H05K2201/10689 ,  H05K2203/1572 ,  Y02P70/611 ,  Y10T29/4913 ,  Y10T29/49144 ,  H01L2924/00

Abstract: A chip module (10) comprising a chip array (14) which includes an interconnect substrate (16) having opposed, generally planar surfaces and a first interconnect pad array (22) disposed on at least one of the surfaces. Attached to the interconnect substrate (16) is at least one integrated circuit chip (34) which is electrically connected to the first interconnect pad array (22). Chip module (10) further comprises a package (12) which comprises a main body (42) defining a cavity sized and configured to receive chip array (14) and having a generally planar interconnect shelf which extends within the cavity and includes a second interconnect pad array disposed thereon. The package (12) also includes a lid (44) attachable to main body (42). The chip array (14) is insertable into the cavity such that the first and second interconnect pad arrays are in aligned contact with each other and the attachment of lid (44) to main body (42) encloses and seals the chip array (14) within package (12).

Abstract translation: 一种芯片模块（10），包括芯片阵列（14），芯片阵列（14）包括具有相对的大致平坦表面的互连基板（16）和设置在至少一个表面上的第一互连焊盘阵列（22）。 连接到互连基板（16）的是至少一个电连接到第一互连焊盘阵列（22）的集成电路芯片（34）。 芯片模块（10）还包括封装（12），其包括主体（42），所述主体（42）限定尺寸和构造成容纳芯片阵列（14）并且具有在所述腔内延伸的大致平面的互连架，并且包括第二互连 垫阵列。 包装（12）还包括可连接到主体（42）的盖（44）。 芯片阵列（14）可插入空腔中，使得第一和第二互连焊盘阵列彼此对准接触，并且盖（44）与主体（42）的附接包围并密封芯片阵列（14） 在包装（12）内。

公开(公告)号：WO00035016A1

公开(公告)日：2000-06-15

申请号：PCT/US1999/028944

申请日：1999-12-07

IPC: H01L25/10 ,  H05K1/18

CPC classification number: H05K1/182 ,  H01L25/105 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multi-chip package includes a substrate having an opening about the central region. At least two integrated circuit chips are mounted on the substrate. The first chip is connected to one side of the substrate, while the second chip is connected to the other side of the substrate. At least a portion of one of the chips is positioned within the opening, and the chips are vertically stacked. The bottom side of the substrate includes a plurality of interconnect bumps for providing electrical connection to a circuit board or other substrate.

Abstract translation: 多芯片封装包括具有围绕中心区域的开口的基板。 至少两个集成电路芯片安装在基板上。 第一芯片连接到基板的一侧，而第二芯片连接到基板的另一侧。 芯片中的一个的至少一部分位于开口内，芯片垂直堆叠。 衬底的底侧包括用于提供与电路板或其它衬底的电连接的多个互连凸块。

公开(公告)号：WO99022570A2

公开(公告)日：1999-05-14

申请号：PCT/RU1998/000359

申请日：1998-11-03

IPC: H01L25/03 ,  H01L25/10 ,  H05K1/18 ,  H05K7/02

CPC classification number: H05K1/189 ,  H01L25/105 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/0002 ,  H05K7/023 ,  H01L2924/00

Abstract: The present invention relates to the conception of three-dimensional modules using naked three-dimension or film-type electronic components. Independent electronic components are formed on the base of IC crystals while micro-boards are used for supporting passive and active electronic components, wherein multi-functional-purpose intermediate boards are mounted between said independent components and micro-boards. All constitutive parts of the module are essentially made of thermally conductive materials and form, together with the members of the heat sink provided inside said module, an efficient heat-dispersion assembly. The micro-boards and the intermediate boards further include film-type active and passive components which are realised according to the semi-conductor, thin-layer or thick-layer techniques. This system is used for substantially increasing the operation capacity of an apparatus. This invention also relates to a module universal structure which can be used in many electronic devices with various purposes. The structure allows this module to be used in severe exploitation conditions and increases the packaging density up to the present industrial limits. This invention also relates to variants for economically and efficiently assembling this module using capillary soldering or resilient members.

Abstract translation: 本发明涉及使用裸三维或薄膜型电子元件的三维模块的概念。 在IC晶体的基底上形成独立的电子部件，而微型板用于支持被动和有源的电子部件，其中多功能用途中间板安装在所述独立部件和微板之间。 模块的所有组成部分基本上由导热材料制成，并且与设置在所述模块内部的散热器的构件一起形成有效的热分散组件。 微板和中间板还包括根据半导体，薄层或厚层技术实现的薄膜型有源和无源部件。 该系统用于显着增加装置的操作能力。 本发明还涉及可用于具有各种目的的许多电子设备中的模块通用结构。 该结构允许该模块在严重的开采条件下使用，并将包装密度提高到目前的工业极限。 本发明还涉及用于使用毛细焊接或弹性构件经济地和有效地组装该模块的变型。

公开(公告)号：WO1998025305A1

公开(公告)日：1998-06-11

申请号：PCT/JP1996003547

申请日：1996-12-04

Applicant: HITACHI, LTD. ,  MIYAMOTO, Toshio ,  NISHIMURA, Asao ,  NOGUCHI, Koki ,  MICHISHITA, Satoshi ,  HORIGUCHI, Masashi ,  KUBO, Masaharu

Inventor： HITACHI, LTD.

IPC: H01L25/11

CPC classification number: H01L25/18 ,  H01L23/4985 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2225/1029 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01055 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/13091 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A semiconductor process for a laminated package that contains a semiconductor chip on which at least a CPU and flash memory are formed and one or more semiconductor chips on which at least DRAMs are formed. The process comprises the steps of: patterning conductive layers formed on the tape carriers so that leads may protrude into device holes on one side and connected to the through holes in tape carriers on the other side; sealing the semiconductor chips with a resin after the leads are bonded to the terminals of the chips for electrical connections; stacking the tape carriers with their through holes aligned and filling conductor in the through holes for electrical connections; and forming external terminals connected with the through holes on one end.

Abstract translation: 一种用于层压封装的半导体工艺，其包含至少形成有CPU和闪速存储器的半导体芯片和至少形成有DRAM的一个或多个半导体芯片。 该方法包括以下步骤：对形成在带状载体上的导电层进行构图，使得引线可以突出到一侧的器件孔中，并与另一侧的带状载体中的通孔连接; 在将引线接合到用于电连接的芯片的端子之后，用树脂密封半导体芯片; 堆叠磁带载体，其通孔对准，并将导体填充在通孔中用于电连接; 并在一端形成与通孔连接的外部端子。

公开(公告)号：WO1998022980A1

公开(公告)日：1998-05-28

申请号：PCT/JP1996003407

申请日：1996-11-21

Applicant: HITACHI, LTD. ,  TSUBOSAKI, Kunihiro ,  MIYAMOTO, Toshio

Inventor： HITACHI, LTD.

IPC: H01L21/60

CPC classification number: H01L23/49572 ,  H01L21/565 ,  H01L23/49816 ,  H01L23/49861 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05548 ,  H01L2224/16245 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2225/1029 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05144

Abstract: A semiconductor chip (2) which is thinner than the substrate (1a) of a tape carrier (1) is placed in a device hole formed in the substrate (1a), and the chip (2) is sealed with a sealing resin (3) so that the front and rear surfaces of the chip (2) can be covered with the resin (3). The position of the chip (2) in the thickness direction of the substrate (1a) is adjusted so that the position can coincide with the stress neutral plane of the entire TCP.

Abstract translation: 将比载带（1）的基板（1a）薄的半导体芯片（2）放置在形成于基板（1a）的装置孔内，用密封树脂（3）密封芯片 ），使得芯片（2）的前表面和后表面可以被树脂（3）覆盖。 调整芯片（2）在基板（1a）的厚度方向上的位置，使得该位置可以与整个TCP的应力中立平面相一致。

公开(公告)号：WO1994023447A1

公开(公告)日：1994-10-13

申请号：PCT/US1994003348

申请日：1994-03-25

Applicant: STAKTEK CORPORATION

Inventor： STAKTEK CORPORATION ,  BURNS, Carmen, D. ,  CADY, James, W. ,  ROANE, Jerry, M. ,  TROETSCHEL, Phillip, Randall

IPC: H01L21/60

CPC classification number: H01L23/49555 ,  H01L23/16 ,  H01L23/31 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/4951 ,  H01L23/49541 ,  H01L23/562 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/48247 ,  H01L2225/1029 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K1/0201 ,  H05K1/181 ,  H05K3/3421 ,  H05K7/023 ,  Y10S438/977 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: The present invention provides a method for fabricating modified integrated circuit packages that are ultra-thin and resist warping. The integrated circuit packages are made thinner by removing some of the casing material (29) uniformly from the upper (23) and lower (32) major surfaces of the integrated circuit package. To prevent the resulting ultra-thin integrated circuit package from warping, a thin layer (41) of material with a coefficient of thermal expansion less than that of silicon is mounted to the upper major surface of the package after some of the casing material has been removed uniformly from the upper major surface. Also, a thin layer (44) of material with a coefficient of thermal expansion greater than that of silicon may be mounted to the lower major surface of the package after some of the casing material has been removed uniformly from the lower major surface. The result is an ultra-thin integrated circuit package that is thermally and mechanically balanced to prevent warping.

Abstract translation: 本发明提供一种制造超薄且抗翘曲的改进的集成电路封装的方法。 通过从集成电路封装的上（23）和下（32）主表面均匀地去除一些外壳材料（29），使集成电路封装件变薄。 为了防止所得到的超薄集成电路封装翘曲，在一些外壳材料已经被覆盖之后，在封装的上主表面上安装了热膨胀系数小于硅的材料的薄层（41） 从上主表面均匀地去除。 此外，在从下主表面均匀地除去一些外壳材料之后，可以将热膨胀系数大于硅的材料的薄层（44）安装到封装的下主表面。 其结果是一种超薄的集成电路封装，其热和机械平衡以防止翘曲。

公开(公告)号：WO2016101151A1

公开(公告)日：2016-06-30

申请号：PCT/CN2014/094665

申请日：2014-12-23

Applicant: INTEL CORPORATION ,  SUN, Zhiyong Simon

Inventor： SUN, Zhiyong Simon

IPC: H01L23/34 ,  H01L23/48 ,  H01L23/528

CPC classification number: H01L23/49503 ,  H01L21/4842 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49506 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49555 ,  H01L25/105 ,  H01L2224/48247 ,  H01L2225/1029 ,  H01L2225/1052 ,  H01L2924/0002 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An integrated package design for a package-on-package product is described that uses wire leads. Some embodiments pertain to a stacked package assembly (101) that includes a first die (120) having a front side and a back side, a die paddle (122) attached to the back side of the first die (120), a plurality of wire leads (112), one end being connected to the front side of the die (120) for connection to an external device, a mold compound (126) encapsulating the first die (120) and at least a portion of the die paddle (122), a land pad (124) cut from the die paddle (122) and supported by the mold compound (126), a second plurality of wire leads (134), one end of the wire leads (134) being connected to the front side of the first die (120) and the other end of the wire leads (134) being connected to the land pad (124), a second die (138) stacked over the die paddle (122) and a third plurality of wire leads (136), one end being connected to the second die (138) and the other end being connected to the land pad (124).

Abstract translation: 描述了一种封装封装产品的集成封装设计，使用导线。 一些实施例涉及包括具有前侧和后侧的第一管芯（120）和连接到第一管芯（120）的后侧的管芯焊盘（122）的堆叠封装组件（101），多个 电线引线（112），一端连接到模具（120）的前侧，用于连接到外部装置;封装第一模具（120）和模板（至少一部分）的模具化合物（126） 122），从模板（122）切割并由模具化合物（126）支撑的焊盘（124），第二多个引线（134），引线（134）的一端连接到 第一管芯（120）的前侧和引线引线（134）的另一端连接到接地焊盘（124），堆叠在管芯焊盘（122）上的第二管芯（138）和第三多个焊丝 引线（136），一端连接到第二管芯（138），另一端连接到接地焊盘（124）。