公开(公告)号：WO2005022591A3

公开(公告)日：2005-10-20

申请号：PCT/US2004026790

申请日：2004-08-18

Applicant: ADVANCED INTERCONNECT TECH LTD ,  ISLAM SHAFIDUL ,  SAN ANTONIO ROMARICO SANTOS

Inventor： ISLAM SHAFIDUL ,  SAN ANTONIO ROMARICO SANTOS

IPC: H01L20060101 ,  H01L21/44 ,  H01L21/48 ,  H01L23/31 ,  H01L23/495 ,  H01L25/10

CPC classification number: H01L21/4832 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L25/105 ,  H01L2221/68377 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32257 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/84439 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/85 ,  H01L2924/0665 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099

Abstract: A semiconductor device package includes an electrically conductive lead frame having a plurality of posts disposed at a perimeter of the package. Each of the posts has a first contact surface disposed at the first package face and a second contact surface disposed at the second package face. The lead frame also includes a plurality of post extensions disposed at the second package face. Each of the post extensions includes a bond site formed on a surface of the post extension opposite the second package face. At least one I/O pads on the semiconductor device is electrically connected to the post extension at the bond site using wirebonding, tape automated bonding, or flip-chip methods. The package can be assembled use a lead frame having pre-formed leads, with or without taping, or it can employ the use of partially etched lead frames. A stack of the semiconductor device packages may be formed.

Abstract translation: 一种半导体器件封装包括导电引线框架，该导电引线框架具有设置在封装周边的多个柱。 每个柱具有设置在第一包装面处的第一接触表面和设置在第二包装面处的第二接触表面。 引线框架还包括设置在第二包装面处的多个支柱延伸部。 每个柱延伸部包括形成在柱延伸部的与第二包装面相对的表面上的结合部位。 半导体器件上的至少一个I / O焊盘使用引线键合，带式自动键合或倒装芯片方法在键合位置处电连接到柱延伸部分。 封装可以使用具有预成型引线的引线框架进行组装，有或没有胶带，或者可以使用部分蚀刻的引线框架。 可以形成半导体器件封装的堆叠。

公开(公告)号：WO2005022591A9

公开(公告)日：2005-06-02

申请号：PCT/US2004026790

申请日：2004-08-18

Applicant: ADVANCED INTERCONNECT TECH LTD ,  ISLAM SHAFIDUL ,  SAN ANTONIO ROMARICO SANTOS

Inventor： ISLAM SHAFIDUL ,  SAN ANTONIO ROMARICO SANTOS

IPC: H01L20060101 ,  H01L21/44 ,  H01L21/48 ,  H01L23/31 ,  H01L23/495 ,  H01L25/10 ,  H01L

CPC classification number: H01L21/4832 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L25/105 ,  H01L2221/68377 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32257 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/84439 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/85 ,  H01L2924/0665 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099

Abstract: A semiconductor device package includes an electrically conductive lead frame having a plurality of posts disposed at a perimeter of the package. Each of the posts has a first contact surface disposed at the first package face and a second contact surface disposed at the second package face. The lead frame also includes a plurality of post extensions disposed at the second package face. Each of the post extensions includes a bond site formed on a surface of the post extension opposite the second package face. At least one I/O pads on the semiconductor device is electrically connected to the post extension at the bond site using wirebonding, tape automated bonding, or flip-chip methods. The package can be assembled use a lead frame having pre-formed leads, with or without taping, or it can employ the use of partially etched lead frames. A stack of the semiconductor device packages may be formed.

Abstract translation: 半导体器件封装包括导电引线框架，其具有设置在封装的周边的多个柱。 每个柱具有设置在第一封装面处的第一接触表面和设置在第二封装面处的第二接触表面。 引线框架还包括设置在第二封装面处的多个柱延伸部。 每个柱延伸部包括形成在与第二封装面相对的柱延伸部的表面上的粘结部位。 半导体器件上的至少一个I / O焊盘使用引线接合，带自动接合或倒装芯片方法在接合位置处电连接到柱延伸部。 封装可以组装使用具有预成形引线的引线框架，带或不带，或者可以使用部分蚀刻的引线框架。 可以形成半导体器件封装的堆叠。

公开(公告)号：WO2008057770A9

公开(公告)日：2008-08-21

申请号：PCT/US2007082423

申请日：2007-10-24

Applicant: UNISEM MAURITIUS HOLDINGS LTD ,  UNISEM SUNNYVALE INC ,  RAMOS MARY JEAN ,  SUBAGIO ANANG ,  SIMPORIOS GUIRIT LYNN ,  SAN ANTONIO ROMARICO SANTOS

Inventor： RAMOS MARY JEAN ,  SUBAGIO ANANG ,  SIMPORIOS GUIRIT LYNN ,  SAN ANTONIO ROMARICO SANTOS

IPC: H01L23/495 ,  H01L21/48

CPC classification number: H01L23/3107 ,  H01L21/4832 ,  H01L21/561 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/16 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/371 ,  H01L2224/37139 ,  H01L2224/37147 ,  H01L2224/37599 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/48711 ,  H01L2224/48739 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48811 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/85205 ,  H01L2224/85411 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01067 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/2075

Abstract: A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging lead-count, wherein the method lends itself to better automation of the manufacturing line and improved quality and reliability of the packages produced therefrom. A major portion of the manufacturing process steps is performed with a partially patterned strip of metal formed into a web-like lead frame on one side so that the web-like lead frame is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is hermetically sealed with an encapsulant. The resultant package being electrically isolated enables strip testing and reliable singulation.

Abstract translation: 一种制造引线框架的方法和具有接近芯片级封装引线计数的部分图案化引线框架封装的方法，其中该方法有助于更好地自动化生产线，并提高由其产生的封装的质量和可靠性。 制造工艺步骤的主要部分是在一侧形成为网状引线框架的部分图案化的金属条进行的，使得网状引线框架也是刚性机械地和坚固的，以在没有变形或变形的情况下执行 芯片级和封装级别的芯片连接和引线键合工艺。 金属引线框架的底侧被图案化以隔离芯片焊盘，并且只有在包括芯片和电线在内的前侧之后，用密封剂气密地密封引线接合触点。 所得的封装电隔离使得能够进行条带测试和可靠的分割。

公开(公告)号：WO2008057770A2

公开(公告)日：2008-05-15

申请号：PCT/US2007082423

申请日：2007-10-24

Applicant: UNISEM MAURITIUS HOLDINGS LTD ,  UNISEM SUNNYVALE INC ,  RAMOS MARY JEAN ,  SUBAGIO ANANG ,  SIMPORIOS GUIRIT LYNN ,  SAN ANTONIO ROMARICO SANTOS

Inventor： RAMOS MARY JEAN ,  SUBAGIO ANANG ,  SIMPORIOS GUIRIT LYNN ,  SAN ANTONIO ROMARICO SANTOS

IPC: H01L23/495 ,  H01L21/48

CPC classification number: H01L23/3107 ,  H01L21/4832 ,  H01L21/561 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/16 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/371 ,  H01L2224/37139 ,  H01L2224/37147 ,  H01L2224/37599 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/48711 ,  H01L2224/48739 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48811 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/85205 ,  H01L2224/85411 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01067 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/2075

Abstract: A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging lead-count, wherein the method lends itself to better automation of the manufacturing line and improved quality and reliability of the packages produced therefrom. A major portion of the manufacturing process steps is performed with a partially patterned strip of metal formed into a web-like lead frame on one side so that the web-like lead frame is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is hermetically sealed with an encapsulant. The resultant package being electrically isolated enables strip testing and reliable singulation.

公开(公告)号：WO2007030345A3

公开(公告)日：2007-11-15

申请号：PCT/US2006033418

申请日：2006-08-28

Applicant: ADVANCED INTERCONNECT TECH LTD ,  ISLAM SHAFIDUL ,  SAN ANTONIO ROMARICO SANTOS ,  SUBAGIO ANANG

Inventor： ISLAM SHAFIDUL ,  SAN ANTONIO ROMARICO SANTOS ,  SUBAGIO ANANG

IPC: H01L23/495 ,  H01L23/10 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/49503 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49548 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/86 ,  H01L24/97 ,  H01L2224/05599 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48739 ,  H01L2224/48744 ,  H01L2224/48755 ,  H01L2224/48764 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83001 ,  H01L2224/83101 ,  H01L2224/85001 ,  H01L2224/85205 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/19107 ,  H01L2224/82 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/86 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/01005

Abstract: A semiconductor device package (10) includes a semiconductor device (20) and an electrically conductive lead frame (22) at least partially covered by a molding compound (18). The electrically conductive lead frame (22) includes a plurality of leads (23) disposed proximate a perimeter of the package (10) and a die pad (30) disposed in a central region formed by the plurality of leads (23). The semiconductor device (20) is attached to the die pad (30), and a portion of the die pad (30) extending outward from the die (20) is roughened to improve adhesion to the molding compound (18). In other aspects, grooves (50, 52) are disposed in die pad (30) surfaces to further promote adhesion of the die pad (30) and to prevent moisture from permeating into the vicinity of the semiconductor chip (20). (Drawing Figure 2)

Abstract translation: 半导体器件封装（10）包括半导体器件（20）和至少部分被模塑料（18）覆盖的导电引线框架（22）。 导电引线框架（22）包括靠近封装（10）的周边设置的多个引线（23）和设置在由多个引线（23）形成的中央区域中的管芯焊盘（30）。 将半导体器件（20）附着到管芯焊盘（30），并且从管芯（20）向外延伸的管芯焊盘（30）的一部分被粗糙化以提高对模制化合物（18）的粘附性。 在其它方面，凹槽（50,52）设置在裸片焊盘（30）表面中以进一步促进裸片焊盘（30）的粘附并防止湿气渗透到半导体芯片（20）的附近。 （图2）

公开(公告)号：WO2005017968A3

公开(公告)日：2006-10-19

申请号：PCT/US2004026152

申请日：2004-08-11

Applicant: ADVANCED INTERCONNECT TECH LTD ,  ISLAM SHAFIDUL ,  LAU DANIEL KWOK ,  SAN ANTONIO ROMARICO SANTOS ,  SUBAGIO ANANG ,  MCKERREGHAN MICHAEL HANNAN ,  LITILIT EDMUNDA GUT-OMEN

Inventor： ISLAM SHAFIDUL ,  LAU DANIEL KWOK ,  SAN ANTONIO ROMARICO SANTOS ,  SUBAGIO ANANG ,  MCKERREGHAN MICHAEL HANNAN ,  LITILIT EDMUNDA GUT-OMEN

IPC: H01L20060101 ,  H01L21/44

CPC classification number: H01L23/3114 ,  H01L21/4832 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L24/81 ,  H01L24/85 ,  H01L24/86 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/05599 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48455 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/78302 ,  H01L2224/78313 ,  H01L2224/78318 ,  H01L2224/81801 ,  H01L2224/85001 ,  H01L2224/85099 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/45139 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00015

Abstract: A lead frame (52, 100, 112) for a semiconductor device (die) package (50, 102, 110) is described. Each of the leads (60) in the lead frame (52, 100, 112) includes an interposer (64) having one end (66) disposed proximate the outer face (58) of the package (50, 102, 110) and another end (68) disposed proximate the die (14). Extending from opposite ends of the interposer (64) are a board connecting post (70) and a support post (74). A bond site (78) is formed on a surface of the interposer (64) opposite the support post (74). Each of the leads (60) is electrically connected to an associated input/output (I/O) pad (80) on the die (14) via wirebonding, tape bonding, or flip-chip attachment to the bond site (78). Where wirebonding is used, a wire electrically connecting the I/O pad (80) to the bond site (78) may be wedge bonded to both the I/O pad (80) and the bond site (78). The support post (74) provides support to the end (68) of the interposer (64) during the bonding and coating processes. (Figure 3)

Abstract translation: 描述了用于半导体器件（管芯）封装（50,102,110）的引线框架（52,100,112）。 引线框架（52,100,112）中的每个引线（60）包括插入件（64），其具有靠近封装（50,102,110）的外表面（58）设置的一端（66）和另一端 靠近模具（14）设置的端部（68）。 从插入器（64）的相对端延伸的是连接柱（70）和支撑柱（74）的板。 在所述插入件（64）的与所述支撑柱（74）相对的表面上形成接合部位（78）。 引线（60）中的每一个通过引线接合，带接合或倒装芯片附接到接合部位（78）而与管芯（14）上的相关联的输入/输出（I / O）焊盘（80）电连接。 在使用引线接合的情况下，将I / O焊盘（80）与接合部位（78）电连接的导线可以与I / O焊盘（80）和焊接部位（78）楔合。 在接合和涂覆过程期间，支撑柱（74）为插入件（64）的端部（68）提供支撑。 （图3）

公开(公告)号：WO2008057770A3

公开(公告)日：2008-05-15

申请号：PCT/US2007/082423

申请日：2007-10-24

Applicant: UNISEM (MAURITIUS) HOLDINGS LIMITED ,  UNISEM (SUNNYVALE), INC. ,  RAMOS, Mary, Jean ,  SUBAGIO, Anang ,  SIMPORIOS GUIRIT, Lynn ,  SAN ANTONIO, Romarico, Santos

Inventor： RAMOS, Mary, Jean ,  SUBAGIO, Anang ,  SIMPORIOS GUIRIT, Lynn ,  SAN ANTONIO, Romarico, Santos

IPC: H01L23/495 ,  H01L21/48

Abstract: A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging lead-count, wherein the method lends itself to better automation of the manufacturing line and improved quality and reliability of the packages produced therefrom. A major portion of the manufacturing process steps is performed with a partially patterned strip of metal formed into a web-like lead frame on one side so that the web-like lead frame is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is hermetically sealed with an encapsulant. The resultant package being electrically isolated enables strip testing and reliable singulation.

公开(公告)号：WO2005022591A2

公开(公告)日：2005-03-10

申请号：PCT/US2004/026790

申请日：2004-08-18

Applicant: ADVANCED INTERCONNECT TECHNOLOGIES LIMITED ,  ISLAM, Shafidul ,  SAN ANTONIO, Romarico, Santos

Inventor： ISLAM, Shafidul ,  SAN ANTONIO, Romarico, Santos

IPC: H01L

CPC classification number: H01L21/4832 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L25/105 ,  H01L2221/68377 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32257 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/84439 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/85 ,  H01L2924/0665 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099

Abstract: A semiconductor device package includes an electrically conductive lead frame having a plurality of posts disposed at a perimeter of the package. Each of the posts has a first contact surface disposed at the first package face and a second contact surface disposed at the second package face. The lead frame also includes a plurality of post extensions disposed at the second package face. Each of the post extensions includes a bond site formed on a surface of the post extension opposite the second package face. At least one I/O pads on the semiconductor device is electrically connected to the post extension at the bond site using wirebonding, tape automated bonding, or flip-chip methods. The package can be assembled use a lead frame having pre-formed leads, with or without taping, or it can employ the use of partially etched lead frames. A stack of the semiconductor device packages may be formed.

Abstract translation: 半导体器件封装包括导电引线框架，该导电引线框架具有设置在封装的周边处的多个柱。 每个柱具有设置在第一包装面处的第一接触表面和设置在第二包装面处的第二接触表面。 引线框架还包括设置在第二包装面处的多个支柱延伸部。 每个柱延伸部包括形成在柱延伸部的与第二包装面相对的表面上的结合部位。 半导体器件上的至少一个I / O焊盘使用引线键合，带式自动键合或倒装芯片方法在键合位置处电连接到柱延伸部分。 封装可以使用具有预成型引线的引线框架进行组装，有或没有胶带，或者可以使用部分蚀刻的引线框架。 可以形成一堆半导体器件封装。

公开(公告)号：WO2005017968A2

公开(公告)日：2005-02-24

申请号：PCT/US2004/026152

申请日：2004-08-11

Applicant: ADVANCED INTERCONNECT TECHNOLOGIES LIMITED ,  ISLAM, Shafidul ,  LAU, Daniel, Kwok ,  SAN ANTONIO, Romarico Santos ,  SUBAGIO, Anang ,  MCKERREGHAN, Michael Hannan ,  LITILIT, Edmunda, Gut-Omen

Inventor： ISLAM, Shafidul ,  LAU, Daniel, Kwok ,  SAN ANTONIO, Romarico Santos ,  SUBAGIO, Anang ,  MCKERREGHAN, Michael Hannan ,  LITILIT, Edmunda, Gut-Omen

IPC: H01L

CPC classification number: H01L23/3114 ,  H01L21/4832 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L24/81 ,  H01L24/85 ,  H01L24/86 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/05599 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48455 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/78302 ,  H01L2224/78313 ,  H01L2224/78318 ,  H01L2224/81801 ,  H01L2224/85001 ,  H01L2224/85099 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/45139 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00015

Abstract: A lead frame (52, 100, 112) for a semiconductor device (die) package (50, 102, 110) is described. Each of the leads (60) in the lead frame (52, 100, 112) includes an interposer (64) having one end (66) disposed proximate the outer face (58) of the package (50, 102, 110) and another end (68) disposed proximate the die (14). Extending from opposite ends of the interposer (64) are a board connecting post (70) and a support post (74). A bond site (78) is formed on a surface of the interposer (64) opposite the support post (74). Each of the leads (60) is electrically connected to an associated input/output (I/O) pad (80) on the die (14) via wirebonding, tape bonding, or flip-chip attachment to the bond site (78). Where wirebonding is used, a wire electrically connecting the I/O pad (80) to the bond site (78) may be wedge bonded to both the I/O pad (80) and the bond site (78). The support post (74) provides support to the end (68) of the interposer (64) during the bonding and coating processes. (Figure 3)

Abstract translation: 描述了一种用于半导体器件（管芯）封装（50,102,110）的引线框架（52,100,112）。 引线框架（52,100,112）中的每个引线（60）包括插入件（64），其具有设置在封装（50,102,110）的外表面（58）附近的一端（66）和另一端 靠近模具（14）设置的端部（68）。 从插入器（64）的相对端延伸的是连接柱（70）和支撑柱（74）的板。 在所述插入件（64）的与所述支撑柱（74）相对的表面上形成接合部位（78）。 引线（60）中的每一个通过引线接合，带接合或倒装芯片附接到接合部位（78）而与管芯（14）上的相关联的输入/输出（I / O）焊盘（80）电连接。 在使用引线接合的情况下，将I / O焊盘（80）与接合部位（78）电连接的导线可以楔形地结合到I / O焊盘（80）和焊接部位（78）。 在接合和涂覆过程期间，支撑柱（74）为插入件（64）的端部（68）提供支撑。 （图3）