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    BODY CONTACT FOR SRAM CELL COMPRISING DOUBLE-CHANNEL TRANSISTORS
    61.
    发明申请
    BODY CONTACT FOR SRAM CELL COMPRISING DOUBLE-CHANNEL TRANSISTORS 审中-公开
    身体接触用于包含双通道晶体管的SRAM单元

    公开(公告)号：WO2010022974A1

    公开(公告)日：2010-03-04

    申请号：PCT/EP2009/006263

    申请日：2009-08-28

    Applicant: ADVANCED MICRO DEVICES, INC. ,  WIRBELEIT, Frank

    Inventor： WIRBELEIT, Frank

    IPC: H01L21/8244 ,  H01L27/11 ,  G11C11/412 ,  H01L21/768 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06

    CPC classification number: H01L27/11 ,  H01L21/76895 ,  H01L27/1104 ,  H01L29/0623 ,  H01L29/105 ,  H01L29/7833

    Abstract: A static RAM cell (250) may be formed on the basis of two double channel transistors (200N, 200P) and a select transistor (200S), wherein a body contact may be positioned laterally between the two double channel transistors in the form of a dummy gate electrode structure (205A), while a further rectangular contact (230) may connect the gate electrodes, the source regions and the body contact, thereby establishing a conductive path to the body regions of the transistors. Hence, compared to conventional body contacts, a very space-efficient configuration may be established so that bit density in static RAM cells may significantly be increased.

    Abstract translation: 可以基于两个双沟道晶体管（200N，200P）和选择晶体管（200S）形成静态RAM单元（250），其中主体接触可以侧向位于两个双通道晶体管之间，形式为 伪栅极电极结构（205A），而另一个矩形触点（230）可以连接栅电极，源极区和体接触，从而建立到晶体管的体区的导电路径。 因此，与常规身体接触相比，可以建立非常空间有效的配置，使得静态RAM单元中的位密度可以显着增加。

    LDMOS TRANSISTOR
    62.
    发明申请
    LDMOS TRANSISTOR 审中-公开
    LDMOS晶体管

    公开(公告)号：WO2009144617A1

    公开(公告)日：2009-12-03

    申请号：PCT/IB2009/052082

    申请日：2009-05-19

    Applicant: NXP B.V. ,  THEEUWEN, Stephan, J., C., H. ,  PEUSCHER, Henk, J. ,  VAN DEN HEUVEL, Rene ,  BRON, Paul

    Inventor： THEEUWEN, Stephan, J., C., H. ,  PEUSCHER, Henk, J. ,  VAN DEN HEUVEL, Rene ,  BRON, Paul

    IPC: H01L29/78 ,  H01L29/45 ,  H01L21/336 ,  H01L29/417 ,  H01L29/40 ,  H01L21/225 ,  H01L23/482 ,  H01L23/532

    CPC classification number: H01L29/7835 ,  H01L21/2257 ,  H01L21/28525 ,  H01L21/76895 ,  H01L23/522 ,  H01L29/402 ,  H01L29/41725 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/66659 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An LDMOS transistor (100) on a substrate (70a, 70b) of a first conductivity type, comprises a source region (10) with a source portion (73) and a drain region (12). The source portion and drain region are of a second conductivity type opposite to the first conductivity type and are mutually connected through a channel region (28) in the substrate over which a gate electrode (14) extends. The drain region comprises a drain contact region (16) and a drain extension region (15) which extends from the channel region (28) towards the drain contact region. The drain contact region is electrically connected to a top metal layer (22) by a drain contact (20), and a poly-Si drain contact layer (80) is arranged as a first contact material in between the drain contact region and the drain contact in a contact opening (51) of a first dielectric layer (52) deposited on the surface of the drain region. The poly-Si drain contact layer comprises a dopant element of the second conductivity type which is diffused therefrom through annealing to form said drain contact region.

    Abstract translation: 在第一导电类型的衬底（70a，70b）上的LDMOS晶体管（100）包括具有源极部分（73）和漏极区域（12）的源极区域（10）。 源区和漏区具有与第一导电类型相反的第二导电类型，并且通过栅极电极（14）延伸的衬底中的沟道区（28）相互连接。 漏极区域包括漏极接触区域（16）和从沟道区域（28）向漏极接触区域延伸的漏极延伸区域（15）。 漏极接触区域通过漏极接触（20）与顶部金属层（22）电连接，并且多晶硅漏极接触层（80）作为第一接触材料布置在漏极接触区域和漏极 在沉积在漏极区域的表面上的第一介电层（52）的接触开口（51）中接触。 多晶硅漏极接触层包括第二导电类型的掺杂元素，其通过退火从其扩散以形成所述漏极接触区域。

    METHODS, STRUCTURES AND DESIGNS FOR SELF-ALIGNING LOCAL INTERCONNECTS USED IN INTEGRATED CIRCUITS
    63.
    发明申请
    METHODS, STRUCTURES AND DESIGNS FOR SELF-ALIGNING LOCAL INTERCONNECTS USED IN INTEGRATED CIRCUITS 审中-公开
    用于集成电路中自对准局部互连的方法，结构和设计

    公开(公告)号：WO2009054936A2

    公开(公告)日：2009-04-30

    申请号：PCT/US2008/011961

    申请日：2008-10-20

    Applicant: TELA INNOVATIONS, INC. ,  SMAYLING, Michael, C. ,  BECKER, Scott, T.

    Inventor： SMAYLING, Michael, C. ,  BECKER, Scott, T.

    IPC: H01L21/8238

    CPC classification number: H01L27/092 ,  G03F1/14 ,  G06F17/5077 ,  H01L21/28518 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/105 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods, structures and designs for self-aligned local interconnects are provided. The method includes designing diffusion regions to be in a substrate. Some of a plurality of gates are designed to be active gates and some of the plurality of gates are designed to be formed over isolation regions. The method includes designing the plurality of gates in a regular and repeating alignment along a same direction, and each of the plurality of gates are designed to have dielectric spacers. The method also includes designing a local interconnect layer between or adjacent to the plurality of gates. The local interconnect layer is conductive and disposed over the substrate to allow electrical contact and interconnection with or to some of the diffusion regions of the active gates. The local interconnect layer is self-aligned by the dielectric spacers of the plurality of gates.

    Abstract translation:

    提供了自对准局部互连的方法，结构和设计。 该方法包括将扩散区域设计为在衬底中。 多个栅极中的一些被设计成有源栅极，并且多个栅极中的一些被设计为形成在隔离区域上方。 该方法包括沿着相同方向以规则且重复对齐的方式设计多个栅极，并且多个栅极中的每一个被设计为具有电介质间隔件。 该方法还包括设计多个栅极之间或与多个栅极相邻的局部互连层。 局部互连层是导电的并且设置在衬底上方以允许与有源栅极的一些扩散区域电接触和互连或者与有源栅极的一些扩散区域互连。 局部互连层由多个栅极的电介质间隔物自对准。

    INTEGRATED CIRCUIT AND METHOD OF MANUFACTURE
    66.
    发明申请
    INTEGRATED CIRCUIT AND METHOD OF MANUFACTURE 审中-公开
    集成电路及其制造方法

    公开(公告)号：WO2006118789A3

    公开(公告)日：2007-11-08

    申请号：PCT/US2006014676

    申请日：2006-04-19

    Applicant: ADVANCED MICRO DEVICES INC ,  CHAN DARIN

    Inventor： CHAN DARIN

    IPC: H01L21/318 ,  H01L21/314 ,  H01L21/768

    CPC classification number: H01L21/3185 ,  H01L21/3145 ,  H01L21/76832 ,  H01L21/76895 ,  H01L21/84 ,  H01L27/1203

    Abstract: An integrated circuit (10, 250) having a plurality of active areas (12, 14, 16) separated from each other by a field region (18) and a method for manufacturing the integrated circuit (10, 250). A first polysilicon finger (20) is formed over the first active area (12) and the field region (18) and a second polysilicon finger (22) is formed over the second active area (16) and the field region (18). A first dielectric layer (168) is formed over the first active area (12) and the field region (18) and a second dielectric layer (170) is formed over the second active area (16) and the portion of the first dielectric layer (168) over the field region (18). A first electrical interconnect (175) is formed over and dielectrically isolated from the first polysilicon finger (20) and a second electrical interconnect (177) is formed over and dielectrically isolated from the second active area (16). The second electrical interconnect (177) is electrically coupled to the second polysilicon finger (22).

    Abstract translation: 具有通过场区（18）彼此分离的多个有源区（12,14,16）的集成电路（10,250）和用于制造集成电路（10,250）的方法。 第一多晶硅指状物（20）形成在第一有源区域（12）上并且场区域（18）之上，并且第二多晶硅指状物（22）形成在第二有源区域（16）和场区域（18）上。 第一介电层（168）形成在第一有源区（12）和场区（18）之上，第二介电层（170）形成在第二有源区（16）上，第一介电层 （168）在场区域（18）上。 第一电互连（175）形成在第一多晶硅指状物（20）的上方并且与第一多晶硅指状物（20）绝缘隔离，并且第二电互连（177）形成在第二有源区（16）之上并与之相互隔离。 第二电互连（177）电耦合到第二多晶硅指状物（22）。

    STRUCTURE AND METHOD FOR MAKING HIGH DENSITY MOSFET CIRCUITS WITH DIFFERENT HEIGHT CONTACT LINES
    68.
    发明申请
    STRUCTURE AND METHOD FOR MAKING HIGH DENSITY MOSFET CIRCUITS WITH DIFFERENT HEIGHT CONTACT LINES 审中-公开
    具有不同高度接触线的高密度MOSFET电路的结构和方法

    公开(公告)号：WO2007082199A2

    公开(公告)日：2007-07-19

    申请号：PCT/US2007/060265

    申请日：2007-01-09

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  ZHU, Huilong

    Inventor： ZHU, Huilong

    IPC: H01L29/76

    CPC classification number: H01L21/28052 ,  H01L21/76889 ,  H01L21/76895 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/78 ,  H01L2924/0002 ,  Y10S257/90 ,  Y10S257/92 ,  H01L2924/00

    Abstract: Embodiments herein present a structure, method, etc. for making high density MOSFET circuits with different height contact lines. The MOSFET circuits comprise a contact line (500, 1300), a gate (310, 1210) situated proximate the contact line (500, 1300). The contact line (500, 1300) comprises a height that is less than the height of the gate (310, 1210). The MOSFET circuits further comprise gate spacers (710, 715, 1610, 1615) situated proximate the gate (310, 1210) and no contact line spacer situated proximate the contact line (500, 1300) and between the contact line (500, 1300) and the gate (310, 1210).

    Abstract translation: 本文的实施例提供了用于制造具有不同高度接触线的高密度MOSFET电路的结构，方法等。 MOSFET电路包括接触线（500,1300），位于接触线（500,1300）附近的栅极（310,1210）。 接触线（500,1300）包括小于门（310,1012）的高度的高度。 MOSFET电路还包括位于栅极（310,1210）附近的栅极间隔物（710,715,1610,1615），并且没有位于接触线（500,1300）附近以及接触线（500,1300）之间的接触线隔离物， 和门（310,1210）。

    INTEGRATED CIRCUIT AND METHOD OF MANUFACTURE
    69.
    发明申请
    INTEGRATED CIRCUIT AND METHOD OF MANUFACTURE 审中-公开
    集成电路及其制造方法

    公开(公告)号：WO2006118789A2

    公开(公告)日：2006-11-09

    申请号：PCT/US2006/014676

    申请日：2006-04-19

    Applicant: ADVANCED MICRO DEVICES, INC. ,  CHAN, Darin

    Inventor： CHAN, Darin

    CPC classification number: H01L21/0217 ,  H01L21/02274 ,  H01L21/3145 ,  H01L21/3185 ,  H01L21/76832 ,  H01L21/76895 ,  H01L21/84 ,  H01L27/1203

    Abstract: An integrated circuit (10, 250) having a plurality of active areas (12, 14, 16) separated from each other by a field region (18) and a method for manufacturing the integrated circuit (10, 250). A first polysilicon finger (20) is formed over the first active area (12) and the field region (18) and a second polysilicon finger (22) is formed over the second active area (16) and the field region (18). A first dielectric layer (168) is formed over the first active area (12) and the field region (18) and a second dielectric layer (170) is formed over the second active area (16) and the portion of the first dielectric layer (168) over the field region (18). A first electrical interconnect (175) is formed over and dielectrically isolated from the first polysilicon finger (20) and a second electrical interconnect (177) is formed over and dielectrically isolated from the second active area (16). The second electrical interconnect (177) is electrically coupled to the second polysilicon finger (22).

    Abstract translation: 具有通过场区（18）彼此分离的多个有源区（12,14,16）的集成电路（10,250）和用于制造集成电路（10,250）的方法。 第一多晶硅指状物（20）形成在第一有源区域（12）上并且场区域（18）上，并且第二多晶硅指状物（22）形成在第二有源区域（16）和场区域（18）上。 第一介电层（168）形成在第一有源区（12）和场区（18）之上，第二介电层（170）形成在第二有源区（16）上，第一介电层 （168）在场区域（18）上。 第一电互连（175）形成在第一多晶硅指状物（20）的上方并且与第一多晶硅指状物（20）绝缘隔离，并且第二电互连（177）形成在第二有源区（16）之上并与之相互隔离。 第二电互连（177）电耦合到第二多晶硅指状物（22）。

    METHODS OF FORMING ELECTRICAL CONNECTIONS FOR SEMICONDUCTOR CONSTRUCTIONS
    70.
    发明申请
    METHODS OF FORMING ELECTRICAL CONNECTIONS FOR SEMICONDUCTOR CONSTRUCTIONS 审中-公开
    形成半导体结构电气连接的方法

    公开(公告)号：WO2005109491A1

    公开(公告)日：2005-11-17

    申请号：PCT/US2005/014951

    申请日：2005-04-28

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： TRAN, Luan, C. ,  FISHBURN, Fred, D.

    IPC: H01L21/768

    CPC classification number: H01L21/7681 ,  H01L21/76895 ,  H01L21/823475

    Abstract: The invention includes methods for forming electrical connections associated with semiconductor constructions. A semiconductor substrate is provided which has a conductive line thereover, and which has at least two diffusion regions adjacent the conductive line. A patterned etch stop is formed over the diffusion regions. The patterned etch stop has a pair of openings extending through it, with the openings being along a row substantially parallel to an axis of the line. An insulative material is formed over the etch stop. The insulative material is exposed to an etch to form a trench within the insulative material, and to extend the openings from the etch stop to the diffusion regions. At least a portion of the trench is directly over the openings and extends along the axis of the line. An electrically conductive material is formed within the openings and within the trench.

    Abstract translation: 本发明包括用于形成与半导体结构相关联的电连接的方法。 提供了一种在其上具有导线的半导体衬底，并且具有与导电线相邻的至少两个扩散区域。 在扩散区域上形成图案化的蚀刻停止层。 图案化蚀刻停止件具有延伸穿过其的一对开口，其中开口沿着大致平行于该线的轴线。 在蚀刻停止点上形成绝缘材料。 绝缘材料暴露于蚀刻以在绝缘材料内形成沟槽，并且将开口从蚀刻停止件延伸到扩散区域。 沟槽的至少一部分直接在开口上方并且沿着线的轴线延伸。 在开口内和沟槽内形成导电材料。

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