公开(公告)号：WO2008085687A3

公开(公告)日：2008-08-28

申请号：PCT/US2007088282

申请日：2007-12-20

Applicant: FREESCALE SEMICONDUCTOR INC ,  HESS KEVIN J ,  LEE CHU-CHUNG ,  WENZEL ROBERT J

Inventor： HESS KEVIN J ,  LEE CHU-CHUNG ,  WENZEL ROBERT J

IPC: H01L23/28

CPC classification number: H01L23/295 ,  H01L21/561 ,  H01L21/568 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/15311

Abstract: A method of packaging a semiconductor (10) includes providing a support structure (12). An adhesive layer (14) is formed overlying the support structure (12) and is in contact with the support structure. A plurality of semiconductor die (16, 18, 20) is placed on the adhesive layer. The semiconductor die are laterally separated from each other and have electrical contacts that are in contact with the adhesive layer. A layer (26) of encapsulating material is formed overlying and between the plurality of semiconductor die and has a distribution of filler material (28). A concentration of the filler material (28) is increased in all areas laterally adjacent each of the plurality of semiconductor die.

Abstract translation: 包装半导体（10）的方法包括提供支撑结构（12）。 形成在支撑结构（12）上方并且与支撑结构接触的粘合剂层（14）。 多个半导体管芯（16,18,20）被放置在粘合剂层上。 半导体管芯相互横向分离并具有与粘合剂层接触的电接触。 封装材料的层（26）形成在多个半导体管芯之间并且在多个半导体管芯之间并且具有填充材料（28）的分布。 填充材料（28）的浓度在与多个半导体管芯中的每一个横向相邻的所有区域中增加。

公开(公告)号：WO2007098306A3

公开(公告)日：2008-10-30

申请号：PCT/US2007060845

申请日：2007-01-22

Applicant: FREESCALE SEMICONDUCTOR INC ,  LEE CHU-CHUNG ,  HESS KEVIN J

Inventor： LEE CHU-CHUNG ,  HESS KEVIN J

IPC: H01L21/44

CPC classification number: H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05624 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2224/48507 ,  H01L2224/48624 ,  H01L2224/48799 ,  H01L2224/85205 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01073 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01201 ,  H01L2924/01327 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/01203 ,  H01L2224/05147 ,  H01L2924/00 ,  H01L2224/48824 ,  H01L2924/01202

Abstract: A bond pad (25) for an electronic device (10) such as an integrated circuit makes electrical connection to an underlying device (14) via an interconnect layer (16). The bond pad has a first layer (24) of a material that is aluminum and copper and a second layer (26), over the first layer (26), of a second material that is aluminum and is essentially free of copper. The second layer (26) functions as a cap to the first layer (24) for preventing copper in the first layer (24) from being corroded by residual chemical elements. A wire (32) such as a gold wire may be bonded to the second layer (26) of the bond pad.

Abstract translation: 用于诸如集成电路的电子设备（10）的接合焊盘（25）经由互连层（16）电连接到下面的设备（14）。 接合焊盘具有铝和铜的材料的第一层（24）和在第一层（26）上的第二材料的第二层（26），第二材料是铝并且基本上不含铜。 第二层（26）用作第一层（24）的盖，用于防止第一层（24）中的铜被残留的化学元素腐蚀。 诸如金线的线（32）可以结合到接合焊盘的第二层（26）。

公开(公告)号：WO2007016088A3

公开(公告)日：2009-04-30

申请号：PCT/US2006028837

申请日：2006-07-25

Applicant: FREESCALE SEMICONDUCTOR INC ,  HESS KEVIN J ,  LEE CHU-CHUNG

Inventor： HESS KEVIN J ,  LEE CHU-CHUNG

IPC: H01L23/28

CPC classification number: H01L23/50 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/552 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/73207 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19043 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor package (10) uses a plurality of thermal conductors (56-64) that extend upward within an encapsulant (16) from one or more thermal bond pads (22, 24, 26) on a die (14) to disperse heat. The thermal conductors may be bond wires or conductive stud bumps and do not extend beyond a lateral edge of the die. One or more of the thermal conductors may be looped within the encapsulant and exposed at an upper surface of the encapsulant. In one form a heat spreader (68) is placed overlying the encapsulant for further heat removal. In another form the heat spreader functions as a power or ground terminal directly to points interior to the die via the thermal conductors. Active bond pads may be placed exclusively along the die's periphery or also included within the interior of the die.

Abstract translation: 半导体封装（10）使用从模具（14）上的一个或多个热粘合垫（22,24,26）在密封剂（16）内向上延伸的多个热导体（56-64）以分散热量。 热导体可以是接合线或导电柱状凸起，并且不延伸超过模具的侧边缘。 一个或多个热导体可以环绕在密封剂内并暴露在密封剂的上表面。 在一种形式中，将散热器（68）放置在所述密封剂上方以进一步除热。 在另一种形式中，散热器用作电源或接地端子，直接通过热导体指向芯片的内部。 主动键合焊盘可以沿模具的周边排列，也可以包括在模具的内部。

公开(公告)号：WO2006115576A2

公开(公告)日：2006-11-02

申请号：PCT/US2006006418

申请日：2006-02-23

Applicant: FREESCALE SEMICONDUCTOR INC ,  YUAN YUAN ,  HESS KEVIN J ,  LEE CHU-CHUNG ,  TRAN TU-ANH ,  WOOSLEY ALAN H

Inventor： YUAN YUAN ,  HESS KEVIN J ,  LEE CHU-CHUNG ,  TRAN TU-ANH ,  WOOSLEY ALAN H

IPC: H01L23/48

CPC classification number: H01L23/3185 ,  H01L21/78 ,  H01L23/3128 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An integrated circuit (10) has a semiconductor substrate (12) and an interconnect layer (14) that mechanically relatively weak and susceptible to cracks and delamination. In the formation of the integrated circuit from a semiconductor wafer, a cut (26) is made through the interconnect layer (14) to form an edge of the interconnect layer. This cut may continue completely through the wafer thickness or stop short of doing so. In either case, after cutting through the interconnect layer, a reconditioning layer (30) is formed on the edge of the interconnect layer. This reconditioning layer seals the existing cracks and delaminations and inhibits the further delamination or cracking of the interconnect layer. The sealing layer may be formed, for example, before the cut through the wafer, after the cut through the wafer but before any packaging, or after performing wirebonding between the interconnect layer and an integrated circuit package.

Abstract translation: 集成电路（10）具有半导体衬底（12）和机械相对较弱并易于发生裂纹和分层的互连层（14）。 在从半导体晶片形成集成电路时，通过互连层（14）制成切口（26），以形成互连层的边缘。 该切割可以完全延续晶片厚度，或者停止这样做。 在任一情况下，在切穿互连层之后，在互连层的边缘上形成再生层（30）。 该修复层密封现有的裂纹和分层，并且抑制互连层的进一步分层或破裂。 密封层可以例如在经过晶片切割之后，经过晶片切割之后，但在任何包装之前，或者在互连层和集成电路封装之间进行引线键合之后形成。

公开(公告)号：WO2004090941A3

公开(公告)日：2005-02-10

申请号：PCT/US2004009816

申请日：2004-03-31

Applicant: FREESCALE SEMICONDUCTOR INC ,  LEE CHU-CHUNG ,  HARUN FUAIDA B ,  HESS KEVIN J ,  TAN LAN CHU ,  YONG CHENG CHOI

Inventor： LEE CHU-CHUNG ,  HARUN FUAIDA B ,  HESS KEVIN J ,  TAN LAN CHU ,  YONG CHENG CHOI

IPC: H01L21/60 ,  H01L23/485 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/85 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05647 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2224/48647 ,  H01L2224/48747 ,  H01L2224/48847 ,  H01L2224/85013 ,  H01L2224/85207 ,  H01L2224/85375 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2224/78 ,  H01L2924/00

Abstract: An integrated circuit die (10) has a copper contact (16, 18), which, upon exposure to the ambient air, forms a native copper oxide. An organic material is applied to the copper contact which reacts with the native copper oxide to form an organic coating (12, 14) on the copper contact in order to prevent further copper oxidation. In this manner, further processing at higher temperatures, such as those greater than 100 degrees Celsius, is not inhibited by excessive copper oxidation. For example, due to the organic coating, the high temperature of the wire bond process does not result in excessive oxidation which would prevent reliable wire bonding. Thus, the formation of the organic coating allows for a reliable and thermal resistance wire bond (32, 34). Alternatively, the organic coating can be formed over exposed copper at any time during the formation of the integrated circuit die to prevent or limit the formation of copper oxidation.

Abstract translation: 集成电路管芯（10）具有铜接触（16,18），其在暴露于环境空气时形成天然氧化铜。 将有机材料施加到与天然氧化铜反应的铜接触处，以在铜接触上形成有机涂层（12,14），以防止进一步的铜氧化。 以这种方式，在较高温度（例如大于100摄氏度的温度）下的进一步处理不会被过量的铜氧化所阻碍。 例如，由于有机涂层，引线键合过程的高温不会导致过度的氧化，这将阻止可靠的引线接合。 因此，有机涂层的形成允许可靠且耐热的引线接合（32,34）。 或者，可以在形成集成电路管芯期间的任何时间在暴露的铜上形成有机涂层，以防止或限制铜氧化的形成。

公开(公告)号：WO2005091760A3

公开(公告)日：2006-01-05

申请号：PCT/US2005002132

申请日：2005-01-21

Applicant: FREESCALE SEMICONDUCTOR INC ,  ZHOU YAPING ,  LEE CHU-CHUNG

Inventor： ZHOU YAPING ,  LEE CHU-CHUNG

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/552 ,  H01L23/58

CPC classification number: H01L24/85 ,  H01L23/49838 ,  H01L23/552 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45166 ,  H01L2224/45184 ,  H01L2224/45565 ,  H01L2224/45684 ,  H01L2224/48091 ,  H01L2224/48464 ,  H01L2224/49111 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/78 ,  H01L2924/00

Abstract: A semiconductor package uses various forms of conductive traces that connect to die bond pads via bond wires. In one form, adjacent bond wires are intentionally crossed around midpoints thereof to reduce self-inductance of the conductors and to minimize self-inductance. In another form, bond wires associated with bond pads having intervening, unrelated bond pads are crossed. Additionally, conductive traces are divided into separate sections and electrically connected by crossed jumper wires or bond wires. Any number of separate sections may be formed for each trace, but an even number is preferable. In another form, one trace is continuous and divides a second trace into two or more sections. The multiple sections are connected by an overlying bond wire. Either insulated or non-insulated bond wire may be used.

Abstract translation: 半导体封装使用各种形式的导电迹线，其通过接合线连接到管芯接合焊盘。 在一种形式中，相邻的接合线有意地绕其中点越过，以减少导体的自感并且使自感最小化。 在另一种形式中，与具有中间的，不相关的键合焊盘的接合焊盘相关联的接合线交叉。 此外，导电迹线被划分成单独的部分，并通过交叉的跨接线或接合线电连接。 可以为每个迹线形成任何数量的分开的部分，但是偶数是优选的。 在另一种形式中，一条迹线是连续的，并将第二条迹线划分成两个或多个部分。 多个部分通过上覆的接合线连接。 可以使用绝缘或非绝缘的接合线。

公开(公告)号：WO2007047058A2

公开(公告)日：2007-04-26

申请号：PCT/US2006037898

申请日：2006-09-27

Applicant: FREESCALE SEMICONDUCTOR INC ,  YUAN YUAN ,  LEE CHU-CHUNG ,  TRAN TU-ANH N ,  WINEBARGER PAUL M

Inventor： YUAN YUAN ,  LEE CHU-CHUNG ,  TRAN TU-ANH N ,  WINEBARGER PAUL M

IPC: B23B19/00

CPC classification number: H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A die (10) for an integrated circuit comprising an active area (22) is provided. The die (10) may further comprise a first ring (12) in a peripheral region of the die (10) at least partially surrounding the active area (22), wherein the first ring (12) may comprise a plurality of polygon shaped cells (32, 36). The die (10) may further comprise a second ring (14) surrounding the first ring (12), wherein the second ring (14) may comprise a plurality of polygon shaped cells (32, 36).

Abstract translation: 提供了一种用于包括有源区域（22）的集成电路的管芯（10）。 模具（10）还可以包括至少部分地围绕有源区域（22）的模具（10）的周边区域中的第一环（12），其中第一环（12）可以包括多个多边形形状的单元 （32,36）。 模具（10）还可以包括围绕第一环（12）的第二环（14），其中第二环（14）可以包括多个多边形形状的单元（32,36）。

公开(公告)号：WO2005017959A3

公开(公告)日：2005-09-09

申请号：PCT/US2004022509

申请日：2004-07-15

Applicant: FREESCALE SEMICONDUCTOR INC ,  TRAN TU-ANH ,  EGUCHI RICHARD K ,  HARPER PETER R ,  LEE CHU-CHUNG ,  WILLIAMS WILLIAM M ,  YONG LOIS

Inventor： TRAN TU-ANH ,  EGUCHI RICHARD K ,  HARPER PETER R ,  LEE CHU-CHUNG ,  WILLIAMS WILLIAM M ,  YONG LOIS

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3187 ,  G11C29/48 ,  G01R31/02

CPC classification number: G11C29/1201 ,  G01R31/2884 ,  G01R31/31715 ,  G01R31/3187 ,  G11C29/48 ,  H01L2224/05554

Abstract: A semiconductor device (10) has a large number of bond pads (24) on the periphery for wirebonding. The semiconductor device (10) has a module (12) as well as other circuitry, but the module (12) takes significantly longer to test than the other circuitry. A relatively small number of the bond pads (20), the module bond pads (20), are required for the module testing due, at least in part, to the semiconductor device having a built-in self-test (BIST) (16) circuitry. The functionality of these module bond pads (22) is duplicated on the top surface of and in the interior of the semiconductor device (10) with module test pads (22) that are significantly larger than the bond pads (24) on the periphery. Having large pads (22) for testing allows longer probe needles, thus increasing parallel testing capability. Duplicating the functionality is achieved through a test pad interface so that the module bond pads (20) and the module test pads (22) do not have to be shorted together.

Abstract translation: 半导体器件（10）在外围具有大量的接合焊盘（24）用于引线接合。 半导体器件（10）具有模块（12）以及其它电路，但是模块（12）需要比其他电路更长的测试时间。 由于至少部分地由具有内置自检（BIST）的半导体器件（BIST）（16），模块测试所需的相对较少数量的接合焊盘（20），模块接合焊盘（20） ）电路。 这些模块接合焊盘（22）的功能性被复制在半导体器件（10）的内表面上和在半导体器件（10）的内部，其中模块测试焊盘（22）明显大于外围的接合焊盘（24）。 具有大的用于测试的焊盘（22）允许更长的探针，因此增加了并行测试能力。 通过测试垫接口实现复制功能，使得模块接合焊盘（20）和模块测试焊盘（22）不必一起短路。