公开(公告)号：WO2012130730A1

公开(公告)日：2012-10-04

申请号：PCT/EP2012/055119

申请日：2012-03-22

Applicant: SOITEC ,  SADAKA, Mariam ,  RADU, Ionut ,  LANDRU, Didier

Inventor： SADAKA, Mariam ,  RADU, Ionut ,  LANDRU, Didier

IPC: H01L21/60 ,  H01L23/485

CPC classification number: H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/0312 ,  H01L2224/03466 ,  H01L2224/0381 ,  H01L2224/03845 ,  H01L2224/03848 ,  H01L2224/03901 ,  H01L2224/05022 ,  H01L2224/05073 ,  H01L2224/05147 ,  H01L2224/05551 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/0805 ,  H01L2224/0807 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/08501 ,  H01L2224/0903 ,  H01L2224/80048 ,  H01L2224/80097 ,  H01L2224/80099 ,  H01L2224/80201 ,  H01L2224/80357 ,  H01L2224/8583 ,  H01L2224/85897 ,  H01L2224/85898 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01067 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/01015 ,  H01L2924/01014 ,  H01L2924/01007 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: Methods of bonding together semiconductor structures include annealing metal of a feature on a semiconductor structure prior to directly bonding the feature to a metal feature of another semiconductor structure to form a bonded metal structure, and annealing the bonded metal structure after the bonding process. The thermal budget of the first annealing process may be at least as high as a thermal budget of a later annealing process. Additional methods involve forming a void in a metal feature, and annealing the metal feature to expand the metal of the feature into the void. Bonded semiconductor structures and intermediate structures are formed using such methods.

Abstract translation: 将半导体结构结合在一起的方法包括在将特征直接接合到另一半导体结构的金属特征之前的半导体结构上的特征的退火金属，以形成接合的金属结构，以及在接合工艺之后使接合的金属结构退火。 第一退火工艺的热预算可以至少等于后续退火工艺的热预算。 附加的方法包括在金属特征中形成空隙，并退火金属特征以将特征的金属扩展到空隙中。 使用这种方法形成结合的半导体结构和中间结构。

公开(公告)号：WO2012131075A1

公开(公告)日：2012-10-04

申请号：PCT/EP2012/055894

申请日：2012-03-30

Applicant: SOITEC ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  SADAKA, Mariam ,  RADU, Ionut ,  LANDRU, Didier ,  DI CIOCCIO, Lea

Inventor： SADAKA, Mariam ,  RADU, Ionut ,  LANDRU, Didier ,  DI CIOCCIO, Lea

IPC: H01L21/60 ,  H01L23/485

CPC classification number: H01L24/03 ,  H01L23/481 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/03452 ,  H01L2224/03464 ,  H01L2224/03466 ,  H01L2224/03845 ,  H01L2224/03848 ,  H01L2224/039 ,  H01L2224/03901 ,  H01L2224/05546 ,  H01L2224/08121 ,  H01L2224/08146 ,  H01L2224/0903 ,  H01L2224/80097 ,  H01L2224/80099 ,  H01L2224/80201 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01067 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2224/034

Abstract: Methods of bonding together semiconductor structures include annealing a first metal feature on a first semiconductor structure, bonding the first metal feature to a second metal feature of a second semiconductor structure to form a bonded metal structure that comprises the first metal feature and the second metal feature, and annealing the bonded metal structure. Annealing the first metal feature may comprise subjecting the first metal feature to a pre-bonding thermal budget, and annealing the bonded metal structure may comprise subjecting the bonded metal structure to a post-bonding thermal budget that is less than the pre-bonding thermal budget. Bonded semiconductor structures are fabricated using such methods.

Abstract translation: 将半导体结构结合在一起的方法包括退火第一半导体结构上的第一金属特征，将第一金属特征结合到第二半导体结构的第二金属特征，以形成包含第一金属特征和第二金属特征 ，并对结合的金属结构进行退火。 退火第一金属特征可以包括使第一金属特征经受预结合热预算，并且对接合的金属结构进行退火可以包括使结合的金属结构经受低于预粘合热预算的后粘合热预算 。 使用这种方法制造粘合的半导体结构。

公开(公告)号：WO2010049497A1

公开(公告)日：2010-05-06

申请号：PCT/EP2009/064308

申请日：2009-10-29

Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES ,  LANDRU, Didier ,  RADU, Ionut ,  VINCENT, Sébastien

Inventor： LANDRU, Didier ,  RADU, Ionut ,  VINCENT, Sébastien

IPC: H01L21/762

CPC classification number: H01L21/187 ,  H01L21/76251

Abstract: The invention relates to a method for producing UTBOX type structures comprising: a) the assembly of a substrate, known as "donor" substrate (1), with a substrate, known as "receiver" substrate (2), at least one of the two substrates comprising an insulating layer (3) of thickness less than 50 nm, b) a first heat treatment for reinforcing the assembly between the two substrates, at temperature below 400°C, carried out during the assembly and/or after assembly, to reinforce said assembly, c) a second heat treatment at temperature above 900°C, the exposure time between 400°C and 900°C being less than 1 minute or 30 seconds.

Abstract translation: 本发明涉及一种用于生产UTBOX型结构的方法，包括：a）将称为“供体”衬底（1）的衬底与称为“接收器”衬底（2）的衬底的组装，至少一个 包括厚度小于50nm的绝缘层（3）的两个基板，b）在组装和/或组装之后执行的在低于400℃的温度下加强两个基板之间的组件的第一热处理， 加强所述组件，c）在高于900℃的温度下的第二次热处理，400℃和900℃之间的曝光时间小于1分钟或30秒。

公开(公告)号：WO2012025532A1

公开(公告)日：2012-03-01

申请号：PCT/EP2011/064481

申请日：2011-08-23

Applicant: SOITEC ,  LANDRU, Didier

Inventor： LANDRU, Didier

IPC: G01N19/04

CPC classification number: G01N19/04

Abstract: The invention relates to a method for measuring a local adhesion energy between two bonded substrates, in a transverse direction, characterized in that it comprises the steps consisting of: - providing that at least one (1) of the two substrates (1, 8) comprise a plurality of elementary test cells (6), each being capable of exerting locally, in the transverse direction, a predetermined mechanical stress (σ) that is a function of the temperature (T), on a bonding interface (10) between the substrates (1, 8), in a direction tending to separate them, - subjecting (21) the substrates to a test temperature, and - identifying (22) zones of the bonding interface (10) showing debonding to deduce from it the local adhesion energy at the test temperature at said zones, the local adhesion energy at a zone of the bonding interface (10) being deduced from the stress exerted by the test cells (6) having caused debonding at said zone.

Abstract translation: 本发明涉及一种用于在横向上测量两个键合衬底之间的局部粘合能的方法，其特征在于，其包括以下步骤： - 提供两个衬底（1,8）中的至少一个（1） 包括多个基本测试电池（6），每个单元测试电池（6）能够在横向上局部地施加作为温度（T）的函数的预定的机械应力，在粘合界面（10）之间 衬底（1,8）沿着倾向于分离它们的方向， - 使（21）衬底处于测试温度，以及 - 识别（22）结合界面（10）的区域，显示脱粘以从其中推断局部粘附 在所述区域处的测试温度下的能量，结合界面（10）的区域处的局部粘附能量是由在所述区域引起脱粘的测试电池（6）施加的应力推导出的。

公开(公告)号：WO2013011372A1

公开(公告)日：2013-01-24

申请号：PCT/IB2012/001406

申请日：2012-07-18

Applicant: SOITEC ,  LANDRU, Didier

Inventor： LANDRU, Didier

IPC: H01L21/762

CPC classification number: B32B43/006 ,  B32B2310/0806 ,  H01L21/76251 ,  H01L21/76254 ,  Y10T156/1158

Abstract: The invention relates to a method for separating a layer (115) from a composite structure (125), the structure comprising a composite stack formed from at least a support substrate (105) which is partially transparent at a determined wavelength, the layer (115) to be separated and a separation layer (110) interposed between the support substrate and the layer to be separated, the method comprising irradiation of the separation layer (110) through the support substrate (105) by means of incident light ray (124a) at the determined wavelength in order to induce weakening or separation by exfoliation of the separation layer, the light ray being inclined so as to form an angle of incidence Θ such that θ>θ min , where θ min = sin -1 (( n 1/n o )sin(tan -1 ( S / 2h ))), n1 and nO respectively being the refractive index of the support substrate and the refractive index of the external medium (130) in contact with the support substrate (105), from which the said ray comes, S being the width of the said ray and h being the thickness of the support substrate. θθθ

Abstract translation: 本发明涉及一种用于从复合结构（125）分离层（115）的方法，所述结构包括由至少一个在确定波长部分透明的支撑衬底（105）形成的复合叠层，所述层（115） ）和介于所述支撑基板和所述待分离层之间的分离层（110），所述方法包括通过入射光线（124a）通过所述支撑基板（105）照射所述分离层（110） 以确定的波长为了通过分离层的剥离而引起弱化或分离，所述光线倾斜以形成入射角T，使得λ>θmin，其中Δmin= sin -1（（n1 / no）sin（tan-1（S / 2h））），n1和n0分别是支撑衬底的折射率和与支撑衬底（105）接触的外部介质（130）的折射率， 所述光线到达，S是所述光线a的宽度 nd h是支撑衬底的厚度。 ???

公开(公告)号：WO2012076618A1

公开(公告)日：2012-06-14

申请号：PCT/EP2011/072122

申请日：2011-12-07

Applicant: SOITEC ,  LANDRU, Didier

Inventor： LANDRU, Didier

IPC: H01L21/762

CPC classification number: H01L21/76254

Abstract: The invention relates to a process for treating a structure semiconductor on insulator comprising a support substrate (1), a layer (2) of oxide or oxynitride of semiconductor material and a thin layer (3) of said semiconductor material. Said process comprises the application of thermal treatment in an atmosphere having fewer than 10 ppm oxygen, and in controlled conditions (temperature, duration), so as to cause at least part of the oxygen of the layer of oxide or oxynitride (2) to be diffused through the thin layer, resulting in decreasing the thickness of oxide or oxynitride in regions (2B) of the layer of oxide or oxynitride (2) distributed according to a determined pattern. Said process comprises the formation on the surface of the thin layer (3) of zones (3B) distributed according to said pattern and exposing a crystallographic orientation different to the rest of the surface (3A) of the thin layer (3).

Abstract translation: 本发明涉及一种用于处理绝缘体上的结构半导体的方法，包括支撑衬底（1），半导体材料的氧化物或氮氧化物的层（2）和所述半导体材料的薄层（3）。 所述方法包括在具有少于10ppm氧气的气氛中和在受控条件（温度，持续时间））中施加热处理，以使氧化物或氮氧化物（2）层的至少一部分氧为 通过薄层扩散，导致根据确定的图案分布的氧化物或氧氮化物（2）层的区域（2B）中的氧化物或氧氮化物的厚度减小。 所述方法包括在根据所述图案分布的区域（3B）的薄层（3）的表面上形成，并暴露与薄层（3）的其余表面（3A）不同的晶体取向。

公开(公告)号：WO2012066021A1

公开(公告)日：2012-05-24

申请号：PCT/EP2011/070220

申请日：2011-11-16

Applicant: SOITEC ,  LANDRU, Didier ,  CAPELLO, Luciana ,  DESBONNETS, Eric ,  FIGUET, Christophe ,  KONONCHUK, Oleg

Inventor： LANDRU, Didier ,  CAPELLO, Luciana ,  DESBONNETS, Eric ,  FIGUET, Christophe ,  KONONCHUK, Oleg

IPC: H01L21/20 ,  H01L21/762

CPC classification number: H05K1/18 ,  H01L21/76251 ,  H01L21/76254

Abstract: The invention relates to an electronic device for radio frequency or power applications, comprising a semiconductor layer supporting electronic components on a support substrate, wherein the support substrate(1) comprises a base layer (12) having a thermal conductivity of at least 30 W/m K and a superficial layer (13, 4) having a thickness of at least 5 µm, said superficial layer (13, 14) having an electrical resistivity of at least 3000 Ohm.cm and a thermal conductivity of at least 30 W/m K. The invention also relates to two processes for manufacturing such a device.

Abstract translation: 本发明涉及一种用于射频或电力应用的电子设备，包括：支撑基板上的电子部件的半导体层，其中所述支撑基板（1）包括具有至少30W / m K和厚度至少为5μm的表层（13,4），所述表面层（13,14）的电阻率至少为3000欧姆·厘米，导热率为至少30瓦/米 本发明还涉及制造这种装置的两个方法。

公开(公告)号：WO2010097294A1

公开(公告)日：2010-09-02

申请号：PCT/EP2010/051701

申请日：2010-02-11

Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES ,  RIOU, Grégory ,  LANDRU, Didier

Inventor： RIOU, Grégory ,  LANDRU, Didier

IPC: H01L21/762

CPC classification number: H01L21/76264 ,  H01L21/76243

Abstract: The invention relates to a method for manufacturing components on a mixed substrate. It comprises the following steps: providing a substrate (1) of the semiconductor-on-insulator (SeOI) type comprising a buried oxide layer (12) between a supporting substrate (11) and a thin layer (13), forming in this substrate (1) a plurality of trenches (3, 3') opening out at the free surface (130) of said thin layer (13) and extending over a depth such that it passes through said thin layer (13) and said buried oxide layer (12), these primary trenches (3, 3') delimiting at least one island (30) of said SeOI substrate (1), forming a mask (4) inside said primary trenches (3, 3') and as a layer covering the areas of the free surface (130) of said thin layer (13) located outside said islands (30), proceeding with heat treatment for dissolving the buried oxide layer present at said island (30), so as to reduce the thickness thereof.

Abstract translation: 本发明涉及一种在混合基板上制造部件的方法。 其包括以下步骤：提供绝缘体上半导体（SeOI）类型的衬底（1），其包括在支撑衬底（11）和薄层（13）之间的掩埋氧化物层（12），在该衬底 （1）在所述薄层（13）的自由表面（130）处开口并在深度上延伸的多个沟槽（3,3'），使得其穿过所述薄层（13）和所述掩埋氧化物层 （12），所述主要沟槽（3,3'）限定所述SeOI衬底（1）的至少一个岛（30），在所述主沟槽（3,3'）内部形成掩模（4），并且覆盖 位于所述岛（30）外部的所述薄层（13）的自由表面（130）的区域，进行用于溶解存在于所述岛（30）处的掩埋氧化物层的热处理，以便减小其厚度。

公开(公告)号：WO2010034696A1

公开(公告)日：2010-04-01

申请号：PCT/EP2009/062219

申请日：2009-09-21

Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES ,  VEYTIZOU, Christelle ,  GRITTI, Fabrice ,  GUIOT, Eric ,  KONONCHUK, Oleg ,  LANDRU, Didier

Inventor： VEYTIZOU, Christelle ,  GRITTI, Fabrice ,  GUIOT, Eric ,  KONONCHUK, Oleg ,  LANDRU, Didier

IPC: H01L21/762

CPC classification number: H01L21/76254 ,  H01L21/76256 ,  H01L2224/05124 ,  H01L2924/00014

Abstract: The invention relates to a process for treating a semiconductor-on- insulator type structure, successively comprising a support substrate (1 ), an oxide layer (2) and a thin semiconductor layer (3), said process comprising the following steps: (a) formation of a silicon nitride or silicon oxinitride mask (4) on the thin semiconductor layer (3), so as to define so-called exposed areas (3a) at the surface of said layer (3), which are not covered by the mask (40, and which are arranged in a desired pattern, (b) application of a heat treatment in a neutral or controlled reducing atmosphere, and under controlled conditions of temperature and time, so as to induce at least a portion of the oxygen of the oxide layer (2) to diffuse through the thin semiconductor layer (3), thereby resulting in the controlled reduction in the oxide thickness in the areas (2a) of the oxide layer corresponding to said desired pattern. In step (a), the mask (4) is formed so as to be at least partially buried in the thickness of the thin semiconductor layer (3).

Abstract translation: 本发明涉及一种处理半导体绝缘体型结构的方法，其连续包括支撑基板（1），氧化物层（2）和薄半导体层（3），所述方法包括以下步骤：（a ）在薄半导体层（3）上形成氮化硅或氮氧化硅掩模（4），以便在所述层（3）的表面处限定所谓的暴露区域（3a），所述暴露区域不被 掩模（40），其以所需图案布置，（b）在中性或受控还原气氛中以及在受控的温度和时间条件下进行热处理，以便诱导至少一部分氧气 所述氧化物层（2）通过所述薄型半导体层（3）扩散，从而导致与所述期望图案相对应的所述氧化物层的区域（2a）中的氧化物厚度的受控降低，在步骤（a）中， 掩模（4）形成为至少部分地埋在第二部分中 e薄半导体层（3）的厚度。

公开(公告)号：WO2009112894A8

公开(公告)日：2009-09-17

申请号：PCT/IB2008/052203

申请日：2008-03-13

Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES ,  ALLIBERT, Frédéric ,  GAUDIN, Gweltaz ,  LALLEMENT, Fabrice ,  LANDRU, Didier ,  LANDRY, Karine ,  SHAHEEN, Mohamad ,  MAZURE, Carlos

Inventor： ALLIBERT, Frédéric ,  GAUDIN, Gweltaz ,  LALLEMENT, Fabrice ,  LANDRU, Didier ,  LANDRY, Karine ,  SHAHEEN, Mohamad ,  MAZURE, Carlos

IPC: H01L29/78

Abstract: The invention relates to a substrate comprising successively a base wafer (1), an insulating layer (2) and a top semiconductor layer (3), characterised in that the insulating layer (2) comprises at least a zone wherein the density of charges is in absolute value higher than 10 10 charges/cm 2 . The invention also relates to a process for making such a substrate.