公开(公告)号：EP2287889A2

公开(公告)日：2011-02-23

申请号：EP10012699.4

申请日：2001-08-27

申请人： Megica Corporation

发明人： Lin, Mou-Shiung

IPC分类号： H01L21/02 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/60 ,  H01L27/08

CPC分类号： H01L28/10 ,  H01L21/768 ,  H01L21/76807 ,  H01L21/76838 ,  H01L23/3192 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/5286 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/60 ,  H01L23/642 ,  H01L23/645 ,  H01L23/647 ,  H01L24/03 ,  H01L24/05 ,  H01L27/0676 ,  H01L27/08 ,  H01L28/20 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/0554 ,  H01L2224/13022 ,  H01L2224/16225 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/15174 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  Y10S257/92 ,  H01L2924/00

摘要： . An integrated circuit chip comprising:
- a silicon substrate;
- a first dielectric layer over said silicon substrate;
- a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer,wherein said metallization structure comprises electroplated copper;
- a second dielectric layer between said first and second metal layers;
- a separating layer over said metallization structure and over said first and second dielectric layers, wherein said separating layer comprises a nitride layer having a thickness between 0.5 and 2 micrometers;
- a third metal layer over said separating layer, wherein said third metal layer comprises at least a portion, vertically over said separating layer, of an inductor, wherein said third metal layer comprises electroplated copper; and
- a first polymer layer over said third metal layer.

摘要翻译： 。 一种集成电路芯片，包括： - 硅衬底; - 在所述硅衬底上的第一介电层; - 在所述第一介电层上的金属化结构，其中所述金属化结构包括第一金属层和在所述第一金属层上的第二金属层，其中所述金属化结构包括电镀铜; - 在所述第一和第二金属层之间的第二介电层; - 在所述金属化结构上并且在所述第一和第二介电层上方的分离层，其中所述分离层包括厚度在0.5和2微米之间的氮化物层; - 在所述分离层上的第三金属层，其中所述第三金属层包括在所述分离层的垂直上方的电感器的至少一部分，其中所述第三金属层包括电镀铜; 和 - 在所述第三金属层上的第一聚合物层。

公开(公告)号：EP2257143A1

公开(公告)日：2010-12-01

申请号：EP09715856.2

申请日：2009-02-24

申请人： Sumitomo Bakelite Co., Ltd.

发明人： MEURA, Toru

IPC分类号： H05K3/34 ,  H05K3/28 ,  H05K3/32 ,  H05K3/36

CPC分类号： H05K3/3436 ,  H01L24/13 ,  H01L24/29 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/0554 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/13022 ,  H01L2224/73104 ,  H01L2224/81193 ,  H01L2224/81204 ,  H01L2224/81801 ,  H01L2224/83191 ,  H01L2224/83855 ,  H01L2224/92 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01059 ,  H01L2924/01072 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/15787 ,  H05K3/305 ,  H05K3/3489 ,  H05K2201/0382 ,  H05K2201/10977 ,  H05K2203/0485 ,  Y02P70/613 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49151 ,  Y10T29/49204 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： The method for providing the solder connection of the present invention is a method for providing a solder connection, which electrically connects a first electronic component having a solder bump to a second electronic component having a protruded electrode to provide electrical connection between the first solder bump and the protruded electrode, wherein a relation of: A + B > C is satisfied, where a height of the first solder bump from one surface of the first electronic component is presented as A [µm], a height of the protruded electrode before the compressive deformation from one surface of the second electronic component is presented as B [µm], and a thickness of the adhesive agent layer is presented as C [µm], and further comprising: disposing the adhesive agent layer in the first electronic component; and deforming the first solder bump and the protruded electrode and providing a contact of the above-described protruded electrode with the above-described first solder bump, so that the sum of the height A [µm] of the first the solder bump and the height B [µm] of the above-described protruded electrode is substantially equivalent to the thickness C [µm] of the above-described adhesive agent layer.

摘要翻译： 提供本发明的焊料连接的方法是一种提供焊接连接的方法，该焊接连接将具有焊料凸块的第一电子部件与具有突出电极的第二电子部件电连接，以提供第一焊料凸块和 突出电极，其中满足以下关系：A + B> C，其中从第一电子部件的一个表面的第一焊料凸块的高度呈现为A [μm]，突出电极在压缩之前的高度 第二电子部件的一个面的变形为B [μm]，粘合剂层的厚度为C [μm]，进一步包括：将粘合剂层设置在第一电子部件中; 并且使第一焊料凸块和突出电极变形，并且提供上述突出电极与上述第一焊料凸块的接触，使得第一焊料凸块的高度A [μm]和高度 上述突出电极的B [μm]基本上等于上述粘合剂层的厚度C [μm]。

公开(公告)号：EP1804287A3

公开(公告)日：2009-10-28

申请号：EP06026978.4

申请日：2006-12-28

申请人： SANYO ELECTRIC CO., LTD. ,  Sanyo Semiconductor Co., Ltd. ,  Sanyo Semiconductor Manufacturing Co., Ltd.

发明人： Kameyama, Koujiro ,  Suzuki, Akira ,  Oikawa, Takahiro

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L21/78

CPC分类号： H01L21/76898 ,  H01L21/78 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/06181 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2924/09701

摘要： The invention is directed to enhancement of reliability and a yield of a semiconductor device by a method of manufacturing the semiconductor device with a supporting body (6) without making the process complex. A second insulation film (9), a semiconductor substrate (1), a first insulation film (2), and a passivation film (4) are etched and removed in this order using a resist layer or a protection layer (20) as a mask. By this etching, an adhesive layer (5) is partially exposed in an opening (21). At this time, a number of semiconductor devices are separated in individual semiconductor dies. Then, a solvent (25) (e.g. alcohol or acetone) is supplied to the exposed adhesive layer (5) through the opening (21) to gradually reduce its adhesion and thereby a supporting body (6) is removed from the semiconductor substrate (1).

摘要翻译： 本发明旨在通过利用支撑体（6）制造半导体器件而不使工艺复杂化的方法提高半导体器件的可靠性和产量。 使用抗蚀剂层或保护层（20）依次蚀刻除去第二绝缘膜（9），半导体基板（1），第一绝缘膜（2）和钝化膜（4） 面具。 通过该蚀刻，粘合剂层（5）部分地暴露在开口（21）中。 此时，在各个半导体管芯中分离出多个半导体器件。 然后，通过开口（21）将溶剂（25）（例如醇或丙酮）供给到暴露的粘合剂层（5），以逐渐降低其粘附力，从而从半导体衬底（1）去除支撑体（6） ）。

公开(公告)号：EP2076922A1

公开(公告)日：2009-07-08

申请号：EP08765221.0

申请日：2008-05-30

申请人： Casio Computer Co., Ltd.

发明人： MIZUSAWA, Aido ,  OKADA, Osamu ,  WAKABAYASHI, Takeshi ,  MIHARA, Ichiro

IPC分类号： H01L23/31 ,  H01L23/485 ,  H01L23/525

CPC分类号： H01L23/3114 ,  H01L23/525 ,  H01L23/5329 ,  H01L23/53295 ,  H01L24/02 ,  H01L24/11 ,  H01L24/12 ,  H01L24/94 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/02331 ,  H01L2224/0401 ,  H01L2224/1147 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/274 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2224/13099 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate (1) on which a structure portion (3) is provided except a peripheral portion thereof, and has a laminated structure including low dielectric films (4) and wiring lines (5), the low dielectric films having a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400°C or higher. An insulating film (9) is formed on the structure portion (3). A connection pad portion is arranged on the insulating film (9) and connected to an uppermost wiring line (5) of the laminated structure portion (3). A bump electrode (13) is provided on the connection pad portion. A sealing film (14) made of an organic resin is provided on a part of the insulating film (9) which surrounds the bump electrode (13). Side surfaces of the laminated structure portion (3) are covered with the insulating film (9) and/or the sealing film (14).

公开(公告)号：EP2008301A2

公开(公告)日：2008-12-31

申请号：EP07760071.6

申请日：2007-04-04

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： EDELSTEIN, Daniel, C. ,  FAROOQ, Mukta, G. ,  HANNON, Robert ,  MELVILLE, Ian, D.

IPC分类号： H01L21/44 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L24/03 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/03019 ,  H01L2224/039 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05083 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/13022 ,  H01L2224/13116 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/01074 ,  H01L2924/00011 ,  H01L2924/00015 ,  H01L2924/01039 ,  H01L2224/05552

摘要： A method for far back end of line (FBEOL) semiconductor device formation includes forming a terminal copper pad (104) in an upper level of a semiconductor wafer (106), forming an insulating stack (114) over the terminal copper pad, and patterning and opening a terminal via (116) within a portion of the insulating stack so as to leave a bottom cap layer of the insulating stack protecting the terminal copper pad. An organic passivation layer (126) is formed and patterned over the top of the insulating stack, and the bottom cap layer (118) over the terminal copper pad is removed. A ball limiting metallurgy (BLM) stack (128) is deposited over the organic passivation layer and terminal copper pad, and a solder ball connection (108) is formed on a patterned portion of the BLM stack.

公开(公告)号：EP1952935A1

公开(公告)日：2008-08-06

申请号：EP07101602.6

申请日：2007-02-01

申请人： HARIMA CHEMICALS, INC.

发明人： Sakurai, Hitoshi ,  Kukimoto, Yoichi

IPC分类号： B23K35/26 ,  B23K35/02 ,  H01L21/60

CPC分类号： B23K35/262 ,  B23K35/0244 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0554 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/11005 ,  H01L2224/11332 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13294 ,  H01L2224/13311 ,  H01L2224/13499 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H05K3/3452 ,  H05K3/3484 ,  H05K2201/0266 ,  H05K2203/043 ,  H05K2203/0568 ,  H05K2203/0588 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A solder paste composition 5 used in a solder precoating method of forming solder bumps by forming a dam 4 around electrodes 2 on a substrate 1, introducing a solder paste composition on the electrodes within openings surrounded by the dam, and heating the solder paste composition introduced, so that solder adheres to the surfaces of the electrodes. The solder paste composition contains solder powder which is of a particle size distribution in which particles having a particle size of below 10 µm are present 16% or more, and the sum of the particles having a particle size of below 10 µm and particles having a particle size of 10 µm or more and below 20 µm is 90% or more. This leads to suppression of the occurrence of bump defects, and to formation of solder bumps of a uniform height with a high yield by a solder precoating method using the dam.

摘要翻译： 通过在基板1上的电极2的周围形成堤坝4，在堤坝包围的开口内的电极上导入焊膏组合物，并将导入的焊膏组合物加热，从而形成焊料凸块的焊料预涂法 ，使得焊料粘附到电极的表面。 该焊膏组合物含有具有粒径分布的焊料粉末，其中粒径小于10μm的粒子存在16％或更多，并且粒径小于10μm的粒子的总和和具有 10μm以上且20μm以下的粒径为90％以上。 这导致抑制了凸块缺陷的发生，并且通过使用该堰的焊料预涂方法以高产率形成了具有均匀高度的焊料凸块。

公开(公告)号：EP1892754A2

公开(公告)日：2008-02-27

申请号：EP07020495.3

申请日：1998-04-28

申请人： Unitive International Limited

发明人： Rinne, Glenn, A. ,  Lizzul, Christine

IPC分类号： H01L21/60

CPC分类号： H01L24/03 ,  H01L23/5286 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0347 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/05599 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13016 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method of electroplating solder bumps on an integrated circuit substrate containing a plurality of active semiconductor devices in the substrate and a plurality of contact pads electrically connected to the active semiconductor devices, comprising the steps of:
forming a plating base layer which electrically shorts the plurality of contact pads together, on the substrate; and
electroplating solder bumps on the plating base layer by drawing plating current vertically through the substrate via a first plurality of parallel electrical paths formed by the plating base layer and the plurality of active semiconductor devices.

公开(公告)号：EP1873819A1

公开(公告)日：2008-01-02

申请号：EP06745367.0

申请日：2006-03-16

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： KITAE, Takashi c/o Matsushita Electric Industrial Co., Ltd. ,  NAKATANI, Seiichi c/o Matsushita Electric Industrial Co., Ltd. ,  KARASHIMA, Seiji c/o Matsushita Electric Industrial Co., Ltd. ,  YAMASHITA, Yoshihisa c/o Matsushita Electric Industrial Co., Ltd. ,  ICHIRYU, Takashi c/o Matsushita Electric Industrial Co., Ltd.

IPC分类号： H01L21/60 ,  H05K3/34

CPC分类号： H01L24/16 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/13 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11001 ,  H01L2224/11003 ,  H01L2224/1141 ,  H01L2224/11502 ,  H01L2224/11522 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13105 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/165 ,  H01L2224/2741 ,  H01L2224/27436 ,  H01L2224/29101 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29291 ,  H01L2224/29299 ,  H01L2224/29305 ,  H01L2224/29309 ,  H01L2224/29311 ,  H01L2224/29313 ,  H01L2224/29316 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/83192 ,  H01L2224/832 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/8388 ,  H01L2224/83885 ,  H01L2224/83886 ,  H01L2224/83887 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1579 ,  H01L2924/381 ,  H01L2924/3841 ,  H05K3/323 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/10977 ,  H05K2203/0264 ,  H05K2203/087 ,  H05K2203/1178 ,  Y02P70/613 ,  H01L2924/01031 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01083 ,  H01L2924/00011 ,  H01L2924/00015 ,  H01L2924/066 ,  H01L2924/06 ,  H01L2924/0675 ,  H01L2924/0695 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： The invention involves mounting a solder resin composition (6) including a solder powder (5a) and a resin (4) on the first electronic component (2); arranging such that the connecting terminals (3) of the first electronic component (2) and the electrode terminals (7) of the second electronic component (8) are facing each other; ejecting a gas (9a) from a gas generation source (1) included in the first electronic component (2) by heating the first electronic component (2) and the solder resin composition; and inducing the flow of the solder powder (5a) in the solder resin composition (6) by inducing convection of the gas (9a) in the solder resin composition (6), and electrically connecting the connecting terminals (3) and the electrode terminals (7) by self-assembly on the connecting terminals (3) and the electrode terminals (7). Through this are provided a flip chip packaging method that enables connecting, with high connection reliability, electrode terminals of a semiconductor chip wired with narrow pitch and connecting terminals of a circuit board, and a bump formation method for packaging on a circuit board.

摘要翻译： 本发明涉及将包含焊料粉末（5a）和树脂（4）的焊料树脂组合物（6）安装在第一电子部件（2）上; 使得第一电子部件（2）的连接端子（3）和第二电子部件（8）的电极端子（7）彼此面对; 通过加热第一电子部件（2）和焊料树脂组合物，从包括在第一电子部件（2）中的气体发生源（1）喷射气体（9a） 并且通过引起焊料树脂组合物（6）中的气体（9a）的对流而引起焊料粉末（5a）在焊料树脂组合物（6）中的流动，并将连接端子（3）和电极端子 （7）通过在连接端子（3）和电极端子（7）上的自组装。 通过这种方式提供了一种倒装芯片封装方法，其能够以高连接可靠性连接具有窄间距的半导体芯片的电极端子和电路板的连接端子，以及用于封装在电路板上的凸块形成方法。

公开(公告)号：EP1801849A2

公开(公告)日：2007-06-27

申请号：EP06026547.7

申请日：2006-12-21

申请人： SANYO ELECTRIC CO. LTD

发明人： Noma, Takashi

IPC分类号： H01L20060101

CPC分类号： H01L27/14618 ,  H01L23/3164 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L27/14687 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/06154 ,  H01L2224/10125 ,  H01L2224/1131 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/14135 ,  H01L2224/14154 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/81141 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15788 ,  H04N5/2257 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00

摘要： The invention provides a package type semiconductor device and a method of manufacturing the same where reliability and yield are enhanced without making a manufacturing process complex. A resin layer (6) and a supporting body (7) are formed on a front surface of a semiconductor substrate (2) formed with a pad electrode (4). Then, the resin layer (6) and the supporting body (7) are removed by etching so as to expose the pad electrode (4). By this etching, the supporting body (7) in two conductive terminal formation regions facing each other over a dicing line (x) and the supporting body in a region connecting with these regions therebetween are simultaneously removed to form an opening (10). Then, a metal layer is formed on the pad electrode (4) exposed in the opening, and a conductive terminal is further formed thereon. Lastly, dicing is performed along the dicing line to separate the semiconductor substrate in individual semiconductor dies.

摘要翻译： 本发明提供一种封装型半导体器件及其制造方法，其可靠性和产率在不使制造工艺复杂化的情况下得到增强。 在形成有焊盘电极（4）的半导体衬底（2）的前表面上形成树脂层（6）和支撑体（7）。 然后，通过蚀刻去除树脂层（6）和支撑体（7），以露出焊盘电极（4）。 通过该蚀刻，同时去除在切割线（x）上彼此面对的两个导电端子形成区域中的支撑体（7）和与其间的这些区域连接的区域中的支撑体，以形成开口（10）。 然后，在露出在开口中的焊盘电极（4）上形成金属层，并且还在其上形成导电端子。 最后，沿着切割线进行切割以分离各个半导体管芯中的半导体衬底。

公开(公告)号：EP1684339A3

公开(公告)日：2007-03-14

申请号：EP06001010.5

申请日：2006-01-18

申请人： SEIKO EPSON CORPORATION

发明人： Nakayama, Hirohisa ,  Sato, Shiro ,  Shoji, Masanobu ,  Nosaka, Hitoshi

IPC分类号： H01L21/60

CPC分类号： H05K3/3489 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/02166 ,  H01L2224/02331 ,  H01L2224/0236 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0381 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/06131 ,  H01L2224/06155 ,  H01L2224/11 ,  H01L2224/1191 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83851 ,  H01L2924/00 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00014

摘要： A method of manufacturing a semiconductor device includes: applying a paste containing acid to an electrical connection section which is electrically connected with a semiconductor substrate; removing the paste from the electrical connection section by washing the electrical connection section; and providing a conductive material to the electrical connection section.