公开(公告)号：EP2068360A2

公开(公告)日：2009-06-10

申请号：EP08169295.6

申请日：2008-11-17

Applicant: E.I. DU PONT DE NEMOURS AND COMPANY

Inventor： Amey, Jr., Daniel, Irwin ,  Borland, William, J.

IPC: H01L23/498 ,  H01L23/50 ,  H01L23/64 ,  H05K1/16

CPC classification number: H05K1/162 ,  H01L2224/16225 ,  H05K1/112 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/09763 ,  H05K2201/10674

Abstract: A printed wiring board semiconductor package (5000) or PWB power core comprising singulated capacitors embedded on multiple layers of the printed wiring board semiconductor package wherein at least a part of each embedded capacitor lies within the die shadow (650) and wherein the embedded, singulated capacitors comprise at least a first electrode (230) and a second electrode (270). The first electrodes and second electrodes of the embedded singulated capacitors are interconnected to the Vcc (power) terminals and the Vss (ground) terminals respectively of a semiconductor device. The size of the embedded capacitors are varied to produce different self-resonant frequencies and their vertical placements within the PWB semiconductor package are used to control the inherent inductance of the capacitor-semiconductor electrical interconnections so that customized resonant frequencies of the embedded capacitors can be achieved with low impedance.

Abstract translation: 一种印刷线路板，半导体封装（5000）或PWB功率芯，其包括嵌入在所述印刷布线板的半导体封装worin至少每个嵌入式电容器的一部分位于管芯遮蔽（650）内的多个层分割电容器和worin嵌入，单片化 电容器包括至少一个第一电极（230）和第二电极（270）。 嵌入单个化的电容器的第一和第二电极电极相互连接，以与Vcc（电源）端子和VSS（接地）端子分别的半导体器件的。 嵌入式电容器的大小被改变，以产生不同的自谐振频率和PWB半导体封装内的垂直刊登位置被用来控制电容器 - 半导体的电互连，从而没有定制的嵌入式电容器的谐振频率的固有电感，可以实现 具有低阻抗。

公开(公告)号：EP1923488A3

公开(公告)日：2009-05-27

申请号：EP08152453.0

申请日：1999-09-14

Applicant: Ibiden Co., Ltd.

Inventor： En, Honchin ,  Nakai, Tohru ,  Oki, Takeo ,  Hirose, Naohiro ,  Noda, Kouta

IPC: H05K3/18 ,  H05K3/46 ,  H05K1/09 ,  C25D5/18 ,  C23C18/34

CPC classification number: H05K3/4644 ,  C23C18/1607 ,  C23C18/1653 ,  C23C18/22 ,  C23C18/30 ,  C23C18/34 ,  C23C18/405 ,  C23C28/00 ,  C23C28/023 ,  C23C28/42 ,  C25D3/38 ,  C25D5/022 ,  C25D5/18 ,  C25D5/34 ,  C25D7/123 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/181 ,  H05K3/241 ,  H05K3/381 ,  H05K3/382 ,  H05K3/384 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4652 ,  H05K3/4661 ,  H05K2201/0215 ,  H05K2201/0344 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/0353 ,  H05K2203/0723 ,  H05K2203/1476 ,  H05K2203/1492 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A process for manufacturing a multilayer printed circuit board comprises a step for providing openings in an interlayer insulating layer (4002), and a step for filling up the openings with a plating metal to construct via holes (4007) and, at the same time, build up an upper-layer conductor layer (4005). The electroplating is performed using an aqueous solution containing a metal ion and 0.1 to 1.5 mmol/L of at least one additive selected from the group consisting of thioureas, cyanides and polyalkylene oxides as a plating solution.

Abstract translation: 用于制造多层印刷电路板的工艺包括在层间绝缘层（4002）中提供开口的步骤以及用电镀金属填充开口以构建通孔（4007）的步骤，并且同时， 建立上层导体层（4005）。 电镀使用含有金属离子和0.1至1.5mmol / L的至少一种选自硫脲，氰化物和聚亚烷基氧化物的添加剂的水溶液作为电镀液来进行。

公开(公告)号：EP1705973A3

公开(公告)日：2009-01-21

申请号：EP06014607.3

申请日：1996-10-23

Applicant: IBIDEN CO., LTD.

Inventor： Kawamura, Yoichiro ,  Murase, Hideki ,  Asai, Motoo

IPC: H05K3/46 ,  H05K3/38

CPC classification number: H05K3/0094 ,  H05K3/382 ,  H05K3/384 ,  H05K3/4602 ,  H05K2201/0129 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09881 ,  H05K2203/0773

Abstract: A build-up multilayer printed circuit board in which an interlaminar insulating layer (2) and a conductor layer (5, 5') are alternately laminated on at least one surface of a wiring substrate (1) having a conductor circuit and a through-hole (9), and the conductor layers (5, 5') are electrically connected to each other through a viahole (7) formed in the interlaminar insulating layer (2), characterized in that a roughened layer (11) is formed on the surface of the conductor in an inner wall of the through-hole (9), and a resin filler comprising a resin and inorganic particles is filled in the through-hole (9) formed in the substrate (1).

Abstract translation: 一种在具有导体电路（4）和通孔（9）的布线基板（1）的表面上交替层叠层间绝缘层和导体层的积层多层印刷电路板，并且导体 层通过形成在层间绝缘层中的通孔彼此电连接，其特征在于，在所述通孔（9）的内壁的导体表面上形成有粗糙层（11）和树脂填料（ 10）填充在形成在布线基板（1）中的通孔（9）中。

公开(公告)号：EP1967876A1

公开(公告)日：2008-09-10

申请号：EP06821810.6

申请日：2006-10-03

Applicant: IBIDEN CO., LTD.

Inventor： KODAMA, Hiroaki ,  YAMADA, Kazuhito

IPC: G02B6/122 ,  H05K1/02 ,  H05K3/10

CPC classification number: G02B6/12002 ,  G02B6/43 ,  H05K1/0274 ,  H05K3/005 ,  H05K3/107 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2203/0108

Abstract: The optical/electrical composite wiring board 10 comprises a lower insulating layer 32 that also serves as a lower clad 22; a upper insulating layer 34 that also serves as an upper clad 24; a core 26 that is placed between the lower insulating layer 32 and the upper insulating layer 34 and has a predetermined optical wiring pattern; and a conductor layer 40 that is placed along with the core 26 between the lower insulating layer 32 and the upper insulating layer 34 and has a predetermined electrical wiring pattern. Herein, the core 26 and the conductor layer 40 are formed via a short manufacturing method, whereby the concave portion for optical wiring 32a and the concave portion for electrical wiring 32b are formed on the lower insulating layer 32 by press process, and a core material and conductor material are filled into each of the concave portions 32a and 32b, and afterward, the core material and conductor material are ground until they are flush with the upper surface of the lower insulating layer 32.

Abstract translation: 光电复合布线板10包括也用作下包层22的下绝缘层32; 也用作上部包层24的上部绝缘层34; 芯26布置在下绝缘层32和上绝缘层34之间并具有预定的光布线图案; 以及导体层40，其与芯26一起放置在下绝缘层32和上绝缘层34之间并具有预定的电布线图案。 这里，通过短的制造方法形成芯26和导体层40，由此通过冲压加工在下绝缘层32上形成用于光布线32a的凹部和电布线32b的凹部，并且芯材 并且将导体材料填充到每个凹部32a和32b中，然后将芯材和导体材料研磨直到它们与下绝缘层32的上表面齐平。

公开(公告)号：EP1445996B1

公开(公告)日：2008-08-20

申请号：EP04011285.6

申请日：1996-10-23

Applicant: IBIDEN CO., LTD.

Inventor： Kawamura, Yoichiro ,  Murase, Hideki ,  Asai, Motoo

IPC: H05K3/46

CPC classification number: H05K3/0094 ,  H05K3/382 ,  H05K3/384 ,  H05K3/4602 ,  H05K2201/0129 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09881 ,  H05K2203/0773

公开(公告)号：EP1906326A1

公开(公告)日：2008-04-02

申请号：EP07102445.9

申请日：2007-02-15

Applicant: FUJITSU LIMITED

Inventor： Ueda, Akira ,  Matsushita, Hideharu

IPC: G06F17/50

CPC classification number: H05K3/0005 ,  G06F17/5018 ,  G06F17/5081 ,  G06F2217/16 ,  G06F2217/80 ,  H05K1/0201 ,  H05K1/115 ,  H05K2201/09536

Abstract: A circuit information acquisition and conversion device, a method, and a program therefor for acquiring a layer (2) (3) configuration, wire traces (2) and shapes of via holes (4) from circuit board design information; optimizing, before conversion into an analysis model, the output target range of the via holes (4) on the basis of a package area, heat density distribution, and power consumption; and creating an analysis model that is suitable for a purpose of the analysis are provided.

Abstract translation: 的电路信息获取和转换装置，方法，及其程序，用于经由从电路板设计信息的孔（4）获取的层（2）（3）的配置，线迹线（2）和形状; 优化，转换前进到分析模型，通过孔的输出目标范围（4）的封装面积，热密度分布和功耗的基础上; 和用于提供该分析的目的模型分析的创建也是合适的。

公开(公告)号：EP1443561A3

公开(公告)日：2008-01-02

申请号：EP04250437.3

申请日：2004-01-28

Applicant: Endicott Interconnect Technologies, Inc.

Inventor： Fraley, Lawrence R. ,  Markovich, Voya R.

IPC: H01L25/065 ,  H01L25/18

CPC classification number: H01L23/145 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/5383 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/06558 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/024 ,  H05K1/113 ,  H05K3/4623 ,  H05K3/4688 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/061 ,  Y10T29/49133 ,  Y10T29/49144 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A multi-chip electronic package (111) which utilizes an organic, laminate chip carrier (300) and a pair of semiconductor chips (77', 77") positioned on an upper surface of the carrier in a stacked orientation. The organic, laminate chip carrier (300) is comprised of a plurality of conductive planes and dielectric layers and couples one or both of the chips to underlying conductors on the bottom surface thereof. The carrier may include a high-speed portion to assure high-frequency connection between the semiconductor chips and may also include an internal capacitor and/or thermally conductive member for enhanced operational capabilities. The first chip (77'), e.g., an ASIC chip, is solder bonded (79) to the carrier (300) while the second chip (77"), e.g., a memory chip, is secured to the first chip's upper surface and coupled to the carrier using a plurality of wirebond connections (113).

公开(公告)号：EP1811823A4

公开(公告)日：2007-11-07

申请号：EP05790482

申请日：2005-10-04

Applicant: IBIDEN CO LTD

Inventor： ASAI MOTOO ,  KODAMA HIROAKI ,  YAMADA KAZUHITO

IPC: H05K1/02 ,  G02B6/00 ,  G02B6/122 ,  G02B6/42 ,  H05K3/46

CPC classification number: G02B6/43 ,  H01L2224/16225 ,  H05K1/0274 ,  H05K3/4623 ,  H05K3/4652 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/061

Abstract: Disclosed is a small-sized multilayer printed wiring board wherein the degree of freedom in design is improved. Such a multilayer printed wiring board is easily applicable to high density wiring. Specifically disclosed is a multilayer printed wiring board wherein a plurality of insulating layers, a conductor circuit and an optical wiring are formed in layers and on which an optical device is mounted. Such a multilayer printed wiring board is characterized in that the optical wiring is formed between the insulating layers.

Abstract translation: 公开了一种小型多层印刷线路板，其中设计的自由度得到改善。 这种多层印刷线路板容易应用于高密度布线。 具体公开了多层印刷布线板，其中多层绝缘层，导体电路和光学布线形成为层并且光学器件被安装在该多层印刷布线板上。 这种多层印刷线路板的特征在于，在绝缘层之间形成光配线。

公开(公告)号：EP1487060A3

公开(公告)日：2007-11-07

申请号：EP04394034.5

申请日：2004-06-11

Applicant: Nortel Networks Limited

Inventor： Kwong, Herman ,  Difilippo, Luigi ,  Wyrzykowska, Aneta

IPC: H05K3/36 ,  H01R12/06

CPC classification number: H01R12/523 ,  H01R12/57 ,  H01R13/642 ,  H01R13/665 ,  H05K3/3436 ,  H05K3/3447 ,  H05K3/365 ,  H05K3/368 ,  H05K3/429 ,  H05K2201/09472 ,  H05K2201/09536 ,  H05K2201/10659 ,  H05K2203/061 ,  Y10T409/300112 ,  Y10T409/300616

Abstract: A circuit device for interconnecting first and second multilayer circuit boards is described herein. The first multilayer circuit board may include a first plurality of electrically conductive vias of varying depths and the second multilayer circuit board may include a second plurality of electrically conductive vias. The circuit device comprises a first plurality of pins located on a first side of the circuit device corresponding to the first plurality of electrically conductive vias of the first multilayer circuit board, each pin having a length compatible with a depth of a respective one of the first plurality of electrically conductive vias of the first multilayer circuit board. The circuit device further comprises a second plurality of pins located on a second side of the circuit device corresponding to the second plurality of electrically conductive vias of the second multilayer circuit board.

公开(公告)号：EP1809083A3

公开(公告)日：2007-07-25

申请号：EP07001746.2

申请日：2002-03-13

Applicant: Ibiden Co., Ltd.

Inventor： Toyoda, Yukihiko ,  Kawamura, Yoichiro ,  Ikeda, Tomoyuki

IPC: H05K3/46 ,  H05K1/11

CPC classification number: H05K1/115 ,  H01L21/486 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0271 ,  H05K1/113 ,  H05K1/116 ,  H05K3/28 ,  H05K3/4602 ,  H05K3/4644 ,  H05K3/4661 ,  H05K3/4688 ,  H05K2201/0133 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/068 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/09745 ,  H01L2924/00

Abstract: A multilayered printed circuit board (200) comprising a substrate and, as serially built up thereon, a conductor circuit and an interlaminar resin insulating layer in an alternate fashion and in repetition, and a solder resist layer (114) formed further thereon as an outermost layer, with a connection of said conductor circuits through said interlaminar resin insulating layer being performed by a via-hole, wherein via-holes in different level layers among said via-holes (1072) are piled on one another, and among said piled via-holes, the via-hole (1071) in the uppermost level has a concave portion formed thereon.

Abstract translation: 一种多层印刷电路板（200），其包括基板和，为顺序建立在其上，导体电路和以交替的方式重复的层间树脂绝缘层和阻焊剂在其上形成进一步作为最外层（114） 层，用的连接通过所述层间树脂绝缘层的导体电路由一个通孔，其中通孔中在不同级别层中的所述通孔（1072）是在彼此堆积执行，并且经由所述堆积中 在最上层的通孔1071上形成有凹部。