公开(公告)号：EP1364788A2

公开(公告)日：2003-11-26

申请号：EP02257528.6

申请日：2002-10-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kim, Jeong-seon ,  Cho, Seo-hyun ,  Son, Dae-woo ,  Kang, Sa-yoon ,  Jung, Myung-song

IPC: B41J2/14

CPC classification number: H05K3/361 ,  B41J2/14072 ,  H05K1/147 ,  H05K3/328 ,  H05K2201/0367 ,  H05K2201/0397 ,  H05K2203/0195

Abstract: An ink jet print head, a method of bonding a flexible printed circuit (FPC) (60) cable for an ink jet print head, and an apparatus adopting the method are provided. In this bonding method, the bonding portion of an FPC conductor (61) is heated being pressed down on a corresponding pad (20) formed on a substrate (10) for an ink jet print head. Then, at least two pads (20) are bonded at a time. In this bonding method, an electrical defect due to pad peel-off phenomenon, which is created by an conventional tape automated bonding (TAB) method in which the conductors of an FPC cable are bonded to the pads on a substrate in a manner where one conductor is bonded to a pad at a time, is removed to increase the reliability of bonding. In addition, the bonding of a plurality of pads (20) at a time leads to a reduction in the time required for bonding.

Abstract translation: 一种喷墨打印头，联结电缆用于喷墨打印头的柔性印刷电路（FPC）（60）的方法，以及装置采用的方法被提供。 在该接合方法中，FPC导体（61）的接合部分加热被按下上的焊盘用于喷墨打印头的基板对应的（20）上形成的（10）。 然后，至少两个垫（20）在一个时间被结合。 在该接合方法中，到电缺陷由于这是由在其中的FPC电缆的导线键合到焊盘上的衬底以这样的方式，其中一个常规的带式自动接合（TAB）方法创建垫剥离现象，在所有 导体在时间接合到垫，被去除以增加键合的可靠性。 此外，在一个时间片的多个（20）的接合导致接合所需的时间的减少。

公开(公告)号：EP0792518B1

公开(公告)日：2003-04-23

申请号：EP95940644.8

申请日：1995-11-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： AKRAM, Salman ,  FARNWORTH, Warren, M. ,  WOOD, Alan, G.

IPC: H01L21/66 ,  G01R1/073

CPC classification number: G01R1/06738 ,  G01R1/07314 ,  H01L2224/13019 ,  H05K1/0306 ,  H05K3/325 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/09045 ,  Y10T29/49155 ,  Y10T29/49453

Abstract: A method for forming a self-limiting, silicon based interconnect for making temporary electrical contact with bond pads on a semiconductor die is provided. The interconnect includes a silicon substrate having an array of contact members adapted to contact the bond pads on the die for test purposes (e.g., burn-in testing). The interconnect is fabricated by: forming the contact members on the substrate; forming a conductive layer on the tip of the contact members; and then forming conductive traces to the conductive layer. The conductive layer is formed by depositing a silicon containing layer (e.g., polysilicon, amorphous silicon) and a metal layer (e.g., titanium, tungsten, platinum) on the substrate and contact members. These layers are reacted to form a silicide. The unreacted metal and silicon containing layer are then etched selective to the conductive layer which remains on the tip of the contact members. Conductive traces are then formed in contact with the conductive layer using a suitable metallization process. Bond wires are attached to the conductive traces and may be attached to external test circuitry. Alternately, another conductive path such as external contacts (e.g., slide contacts) may provide a conductive path between the conductive traces and external circuitry. The conductive layer, conductive traces and bond wires provide a low resistivity conductive path from the tips of the contact members to external test circuitry.

公开(公告)号：EP1081991A3

公开(公告)日：2003-04-02

申请号：EP00307577.7

申请日：2000-09-01

Applicant: SEIKO EPSON CORPORATION

Inventor： Furihata, Hiroaki

IPC: H05K3/36 ,  H05K3/46 ,  G02F1/13

CPC classification number: H05K3/4635 ,  G02F1/13452 ,  H05K1/0393 ,  H05K3/28 ,  H05K3/323 ,  H05K3/361 ,  H05K3/4617 ,  H05K2201/0367 ,  H05K2203/1572

Abstract: The invention provides a flexible wiring board which is of high productivity and low cost, while permitting a wiring pattern to be miniaturized, and to provide an electrooptical device and electronic equipment, each incorporating the flexible wiring board. A flexible wiring board 100 includes a first single-sided flexible board 10 and a second single-sided flexible board 20. The first single-sided flexible board 10 includes a first base body 12 having an insulative property, and a first wiring layer 14 formed in a predetermined pattern on the first base body. The second single-sided flexible board 20 includes a second base body 22 having an insulative property, and a second wiring layer 24 formed in a predetermined pattern on the second base body. The first and second single-sided flexible boards respectively have insulating layers 16 and 26 covering the wiring layers 14 and 24, and the insulating layers are provided with contact sections C10 and C20 respectively. The first single-sided flexible board 10 and the second single-sided flexible board 20 are arranged so that the first wiring layer and the second wiring layer face each other, and are bonded through an anisotropically conductive adhesive layer 30.

公开(公告)号：EP0823732B1

公开(公告)日：2001-11-07

申请号：EP96112701.6

申请日：1996-08-07

Applicant: NITTO DENKO CORPORATION

Inventor： Takayama, Yoshinari, c/o Nitto Denko Corp. ,  Ouchi, Kazuo, c/o Nitto Denko Corp. ,  Hino, Atsushi, c/o Nitto Denko Corp.

IPC: H01L23/498

CPC classification number: H05K3/4007 ,  H01L23/49811 ,  H01L23/4985 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311 ,  H05K3/0035 ,  H05K3/0055 ,  H05K3/423 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/09745 ,  H05K2203/0369 ,  H05K2203/095 ,  H05K2203/1572 ,  H01L2924/00

公开(公告)号：EP1104226A1

公开(公告)日：2001-05-30

申请号：EP99933149.9

申请日：1999-07-29

Applicant: Sony Chemicals Corporation

Inventor： HISHINUMA, Hiroyuki, Sony Chemicals Corp. ,  KURITA, Hideyuki, Sony Chemicals Corp. ,  ITO, Ryo, Sony Chemicals Corp. ,  NAKAMURA, Masayuki, Sony Chemicals Corp.

IPC: H05K3/34 ,  H05K3/28

CPC classification number: H05K3/4007 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/4985 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K3/423 ,  H05K3/4647 ,  H05K2201/0154 ,  H05K2201/0195 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0759 ,  Y10T29/49121 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49155 ,  H01L2224/05624 ,  H01L2924/00014

Abstract: A process for manufacturing a flexible wiring board according to the present invention comprises growing metal bumps 16 using a mask film patterned by photolithography. Fine openings can be formed with good precision, therefore, fine metal bumps 16 can be formed with good precision because laser beam is not used to form openings in a polyimide film. After metal bumps 16 have been formed, the mask film is removed and a liquid resin material is applied and dried to form a coating, which is then cured into a resin film. The coating can be etched at surface portions during coating stage to expose the tops of metal bumps 16.

Abstract translation: 根据本发明的制造柔性布线板的方法包括使用通过光刻图案化的掩模膜生长金属凸块16。 可以精确地形成精细的开口，因此，由于激光束不用于在聚酰亚胺膜中形成开口，因此可以以高精度形成细小的金属凸块16。 在形成金属凸块16之后，去除掩模膜并施加液体树脂材料并干燥以形成涂层，然后将其固化成树脂膜。 涂层可以在涂覆阶段的表面部分进行蚀刻，以露出金属凸块16的顶部

公开(公告)号：EP1035579A3

公开(公告)日：2001-03-07

申请号：EP00301804.1

申请日：2000-03-06

Applicant: Altera Corporation

Inventor： Anderson, Sidney Larry

IPC: H01L23/498

CPC classification number: H01L24/32 ,  H01L21/4853 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05559 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13023 ,  H01L2224/16237 ,  H01L2224/274 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/8547 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K1/112 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09745 ,  H05K2201/10734 ,  H05K2203/041 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49204 ,  H01L2924/00012 ,  H01L2924/207 ,  H01L2924/0133 ,  H01L2924/01049 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/13111 ,  H01L2224/05552 ,  H01L2224/45015 ,  H01L2224/45099

Abstract: An integrated circuit package is provided with a ball landing area having a conductive structure for interlocking a conductive ball to the ball pad. The conductive structure improves the attachment strength between an integrated circuit package and an printed circuit board. In an exemplary embodiment, the locking structure is a conductive material added to the surface of the ball pad to provide a nonplanar interface, such as a dome or a step, which interlocks the conductive ball to the ball pad. The improved package construction increases the area of contact, moves the shear plane to a higher and larger portion on the conductive ball, and/or prevents a crack from propagating along a flat plane across the ball joint. This package construction maintains the small size of the ball land areas and the package, increases the life of the integrated circuit package, while offsetting the problem of package warpage.

公开(公告)号：EP1035580A2

公开(公告)日：2000-09-13

申请号：EP00301805.8

申请日：2000-03-06

Applicant: Altera Corporation

Inventor： Anderson, Sidney Larry ,  Long, Jon ,  Fritz, Donald S.

IPC: H01L23/498 ,  H01L21/58 ,  H01L23/31

CPC classification number: H01L24/32 ,  H01L21/4853 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/16237 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K1/112 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09745 ,  H05K2201/10734 ,  H05K2203/041 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2224/0401 ,  H01L2924/00012

Abstract: An integrated circuit package is constructed to potential reduce stress and damage to an integrated circuit die. A rigid transition medium (220) is attached using adhesive layers (215, 42) and interfaces between a tape carrier (260) and the integrated circuit die (210). The integrated circuit package prevents damage such as die cracks and also enhances the service life of the packaged integrated circuit part.

Abstract translation: 构建集成电路封装，以减少对集成电路管芯的压力和损坏。 刚性过渡介质（42）使用粘合剂层（38,40）和带状载体（20）与集成电路管芯（18）之间的界面附接。 集成电路封装可防止诸如裸片裂纹的损坏，并且还增强了封装集成电路部件的使用寿命。

公开(公告)号：EP1018154A1

公开(公告)日：2000-07-12

申请号：EP98945341.0

申请日：1998-09-22

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE

Inventor： MARION, François ,  MARION, Dominique ,  OUVRIER-BUFFET, Jean-Louis

IPC: H01L21/60 ,  H01L23/485 ,  H01L27/146

CPC classification number: H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/1147 ,  H01L2224/13019 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/16058 ,  H01L2224/16112 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/3511 ,  H05K3/3436 ,  H05K2201/0367 ,  H05K2201/2036 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2224/29099

Abstract: System of components for hybridization including a first component (410) with a first set of hybridization studs (414), and at least a second component (412) with second hybridization studs (450), the first and second studs being respectively associated in pairs of studs, one of the first and one of the second studs, with at least one pair of studs, equipped with a projection (418) of meltable material and the other aforesaid first and second studs of the pair of studs, referred to as contact studs (450, 450a, 450b), having a surface wettable by the meltable material. According to the invention at least one part of the contact stud (450) forms a protuberance (452).Application to manufacturing of electronic, electro-optic and mechanical components.

公开(公告)号：EP0818946A3

公开(公告)日：1999-11-03

申请号：EP97305014.9

申请日：1997-07-08

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Matsuno, Yukio

IPC: H05K3/46 ,  H05K3/40

CPC classification number: H05K1/113 ,  H05K1/095 ,  H05K3/0094 ,  H05K3/181 ,  H05K3/247 ,  H05K3/4007 ,  H05K3/429 ,  H05K3/4685 ,  H05K2201/035 ,  H05K2201/0367 ,  H05K2201/09436 ,  H05K2201/0959 ,  H05K2203/072

Abstract: A printed-wiring board has a copper foil (the first conductive layer) providing electric conductivity formed on one or both sides of an insulating board providing electrical insulation, an insulating layer providing electrical insulation formed at specific sites (where there are through-holes) on the first conductive layer, and a second conductive layer providing electric conductivity formed on the insulating layer. In this printed-wiring board, when the second conductive layer is formed, deposition of an electrically conductive material by plating, and polishing of the deposited electrically conductive material, these steps are repeated at least once, so that the surface of the second conductive layer can be smoothened to enhance the bonding stability of chip parts.

Abstract translation: 印刷电路板具有提供导电性的铜箔（第一导电层），其形成在提供电绝缘的绝缘板的一侧或两侧上，提供在特定位置（其中存在通孔）形成的电绝缘的绝缘层， 以及形成在绝缘层上的提供导电性的第二导电层。 在该印刷电路板中，当形成第二导电层时，通过电镀沉积导电材料并抛光沉积的导电材料，这些步骤重复至少一次，使得第二导电层的表面 可以平滑化，以提高芯片部件的粘合稳定性。

公开(公告)号：EP0932193A2

公开(公告)日：1999-07-28

申请号：EP99101055.4

申请日：1999-01-22

Applicant: RICOH MICROELECTRONICS CO., LTD.

Inventor： Kinoshita, Makoto

IPC: H01L21/60 ,  H01L23/485

CPC classification number: H01L24/11 ,  H01L24/13 ,  H01L2224/10165 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/8114 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K3/1233 ,  H05K3/207 ,  H05K2201/0367 ,  H05K2203/0113 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method of forming a plurality of bump electrodes en bloc on a bump electrode formation surface of a wafer from which chips are to be separated, or on an upper surface of a plurality of chips which are separated from a wafer and placed side by side, the upper surface constituting a bump electrode formation surface, is disclosed.

Abstract translation: 一种将多个凸起电极整体形成在要从其分离的晶片的凸起电极形成表面上或者在与晶片分离并且并排放置的多个芯片的上表面上的方法， 公开了构成凸块电极形成面的上表面。