公开(公告)号：EP1265467A3

公开(公告)日：2004-10-27

申请号：EP02253946.4

申请日：2002-06-06

Applicant: NGK INSULATORS, LTD.

Inventor： Takeuchi, Yukihisa, I.P.D. NGK Insulators, Ltd. ,  Tsuji, Hiroyuki, I.P.D. NGK Insulators, Ltd. ,  Kitamura, Kazumasa, I.P.D. NGK Insulators, Ltd. ,  Yamaguchi, Yoshinori, I.P.D. NGK Insulators, Ltd.

IPC: H05K3/00 ,  H05K3/46 ,  B26F1/02

CPC classification number: B32B38/04 ,  B26F1/02 ,  B26F2210/08 ,  B32B2038/047 ,  B32B2457/08 ,  H05K3/005 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/4638 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/0195 ,  H05K2203/1476 ,  H05K2203/167

Abstract: A perforation of a multilayer board has a surface-profile precision of 8 µm or less, and the ratio of a diameter or the minimum distance between the opposing edges on the opening surface thereof to the axial length is preferably from about 1 : 1 to 1 : 15. The multilayer board is fabricated by a punching machine comprising a punch (10) and a stripper (11) such that a required number of plates are prepared, the first plate (3) is perforated by the punch (10) and is pulled up by closely attaching it to the stripper (11) while leaving the punch (10) in the first bore, the second plate (3) is perforated by the punch (10) and is pulled up together with the first plate (3) while leaving the punch (10) in the second bore, and subsequently, the following plates (3) are perforated by the punch (10) and the perforated plates (3) are stacked along the punch (10) serving as a stacking axis sequentially.

公开(公告)号：EP1443561A2

公开(公告)日：2004-08-04

申请号：EP04250437.3

申请日：2004-01-28

Applicant: Endicott Interconnect Technologies, Inc.

Inventor： Fraley, Lawrence R. ,  Markovich, Voya R.

IPC: H01L25/065 ,  H01L25/18

CPC classification number: H01L23/145 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/5383 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/06558 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/024 ,  H05K1/113 ,  H05K3/4623 ,  H05K3/4688 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/061 ,  Y10T29/49133 ,  Y10T29/49144 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A multi-chip electronic package (111) which utilizes an organic, laminate chip carrier (300) and a pair of semiconductor chips (77', 77") positioned on an upper surface of the carrier in a stacked orientation. The organic, laminate chip carrier (300) is comprised of a plurality of conductive planes and dielectric layers and couples one or both of the chips to underlying conductors on the bottom surface thereof. The carrier may include a high-speed portion to assure high-frequency connection between the semiconductor chips and may also include an internal capacitor and/or thermally conductive member for enhanced operational capabilities. The first chip (77'), e.g., an ASIC chip, is solder bonded (79) to the carrier (300) while the second chip (77"), e.g., a memory chip, is secured to the first chip's upper surface and coupled to the carrier using a plurality of wirebond connections (113).

Abstract translation: 一种多层芯片电子封装（111），其利用位于所述载体的上表面上的层叠取向的有机层压芯片载体（300）和一对半导体芯片（77'，77“），所述有机层压体 芯片载体（300）由多个导电平面和电介质层组成，并且将芯片中的一个或两个耦合到其底表面上的下面的导体，载体可以包括高速部分，以确保高频部分 半导体芯片，还可以包括用于增强操作能力的内部电容器和/或导热构件，第一芯片（77'）例如ASIC芯片被焊接到载体（300）上，而第二芯片 （77“），例如存储芯片，被固定到第一芯片的上表面，并且使用多个引线键合连接（113）耦合到载体。

公开(公告)号：EP1434474A3

公开(公告)日：2004-08-04

申请号：EP03394086.7

申请日：2003-09-12

Applicant: Nortel Networks Limited

Inventor： Duxbury, Guy ,  Kwong, Herman ,  Wyrczykowska, Aneta ,  Difilippo, Luigi G.

IPC: H05K1/11 ,  H05K3/46 ,  H01L23/498

CPC classification number: H05K1/115 ,  H05K1/0298 ,  H05K1/112 ,  H05K3/0005 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09227 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/10734

Abstract: A technique for electrically interconnecting electrical signals between an electronic component and a multilayer signal routing device is disclosed. In one particular exemplary embodiment, the technique may be realized as an interconnect array (200) for electrically interconnecting electrical signals between an electronic component and a multilayer signal routing device having a plurality of electrically conductive signal path layers. In such a case, the interconnect array (200) comprises a plurality of electrically conductive contacts (202) grouped into a plurality of arrangements of electrically conductive contacts (202), wherein each of the plurality of arrangements of electrically conductive contacts (202) are separated from other adjacent ones of the plurality of arrangements of electrically conductive contacts (202) by a channel (206,208) that is correspondingly formed in the multilayer signal routing device such that an increased number of electrical signals may be routed therein on the plurality of electrically conductive signal path layers.

公开(公告)号：EP1404167A1

公开(公告)日：2004-03-31

申请号：EP02743790.4

申请日：2002-07-03

Applicant: NITTO DENKO CORPORATION

Inventor： NAKAMURA, Kei, c/o Nitto Denko Corporation ,  TANIGAWA, Satoshi, c/o Nitto Denko Corporation ,  OOTA, Shinya, c/o Nitto Denko Corporation

IPC: H05K3/46 ,  H05K3/40

CPC classification number: H05K3/462 ,  H05K3/4038 ,  H05K3/4623 ,  H05K2201/0305 ,  H05K2201/09536 ,  H05K2203/0425 ,  Y10T156/10

Abstract: A method of producing a multilayer wired circuit board that can provide sufficient adhesion strength of the interface between a conductor layer and a thermosetting adhesive layer laminated, to provide improvement in connection strength between the conductor layers and thus improvement in reliability. In this method, after a thermosetting adhesive layer is formed on a first conductor layer, an opening is formed in the thermosetting adhesive layer and solder powders are charged in the opening at normal temperature. Sequentially, a second conductor layer is formed on the thermosetting adhesive layer including the opening filled with the solder powders. Thereafter, the solder powders are melted by heating, to electrically connect between the first conductor layer and the second conductor layer.

公开(公告)号：EP1162867A4

公开(公告)日：2004-03-24

申请号：EP00964763

申请日：2000-10-10

Applicant: IBIDEN CO LTD

Inventor： KAWASAKI YOGO ,  SATAKE HIROAKI ,  IWATA YUTAKA ,  TANABE TETSUYA

IPC: H01L23/498 ,  H05K1/11 ,  H05K3/00 ,  H05K3/34 ,  H05K3/38 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K1/113 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K3/0055 ,  H05K3/0094 ,  H05K3/3457 ,  H05K3/381 ,  H05K3/382 ,  H05K3/426 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/0209 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/0796 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/05599

Abstract: Through holes (36) are formed in such a manner as to extend through a core board (30) and lower layer interlayer resin insulator layers (50), while via holes (66) are formed immediately above through holes (66). As a result, the through hole (36) and via hole (66) are in line with each other, so that the wiring length is shortened and the speed of transmission of signals can be increased. Further, since the through hole (36) and the via hole (66) connected to a solder bump (76) (conductive connecting pin (78)) are directly connected, the arrangement is superior in connection reliability.

公开(公告)号：EP1194022A4

公开(公告)日：2004-03-17

申请号：EP00931571

申请日：2000-05-25

Applicant: IBIDEN CO LTD

Inventor： ASAI MOTOO ,  WANG DONGDONG ,  MORI TAKAHIRO

IPC: H01L21/48 ,  H01L23/498 ,  H05K1/03 ,  H05K3/00 ,  H05K3/10 ,  H05K3/18 ,  H05K3/38 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K3/423 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/036 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/181 ,  H05K3/381 ,  H05K3/385 ,  H05K3/387 ,  H05K3/388 ,  H05K3/426 ,  H05K3/427 ,  H05K3/4602 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09736 ,  H05K2201/09881 ,  H05K2203/0315 ,  H05K2203/0733 ,  H05K2203/0773 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/05599

Abstract: A multilayer printed wiring board in which the strength is ensured by sandwiching a metal layer (18) between insulating layers (14, 20), thereby a core sheet (30) can be thin, and the thickness of the multilayer printed wiring board is reduced. Moreover, since a blind hole (22) extending to the metal layer (18) is formed only in insulating layers (14, 20), the fine blind hole (22) can easily be made by a laser beam, and a through hole (36) having a small diameter can be formed.

公开(公告)号：EP0851724B1

公开(公告)日：2003-10-22

申请号：EP97122824.2

申请日：1997-12-23

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： Tsukamoto, Masahide

IPC: H05K3/40 ,  H05K3/46 ,  H05K3/20 ,  H01L23/498 ,  H01L23/31 ,  H01L21/60

CPC classification number: H01L24/80 ,  H01L23/3107 ,  H01L23/49827 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K1/115 ,  H05K3/007 ,  H05K3/20 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/462 ,  H05K3/4623 ,  H05K3/4658 ,  H05K2201/0367 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/0152 ,  H05K2203/1461 ,  Y10T29/49126 ,  Y10T29/49165 ,  Y10T29/49345 ,  H01L2924/00

公开(公告)号：EP1320109A1

公开(公告)日：2003-06-18

申请号：EP02017813.3

申请日：2002-08-07

Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA

Inventor： Yamagata, Kousaku, Mitsubishi Denki Kabushiki K.

IPC: H01F17/00 ,  H01F41/04

CPC classification number: H05K1/165 ,  H01F17/0013 ,  H01F41/045 ,  H05K2201/0715 ,  H05K2201/09536 ,  H05K2201/097

Abstract: On each surface of a dielectric substrate (1b), arranged are a first conductor line pattern (12, 22) having a plurality of first line segments (12a-12c, 22a-22f) and a second conductor line pattern (13, 23) having a plurality of second line segments (13a-13c, 23a-23f). Ends of each first conductor line segment overlap the second conductor line segments, and the first and second line segments are connected via through-holes (14a-14e, 24), thereby forming a single spiral conductor line. Each second conductor line segment for connecting adjacent first conductor line segments has a pair of end parts connected to the first conductor line segments via through-holes and a halfway part having a smaller width.

Abstract translation: 在电介质基板（1b）的每个表面上，布置有具有多个第一线段（12a-12c，22a-22f）和第二导线图案（13,23）的第一导体线图案（12,22） 具有多个第二线段（13a-13c，23a-23f）。 每个第一导体线段的端部与第二导体线段重叠，并且第一和第二线段通过通孔（14a-14e，24）连接，从而形成单个螺旋导体线。 用于连接相邻的第一导体线段的每个第二导体线段具有通过通孔连接到第一导体线段的一对端部和具有较小宽度的中间部分。

公开(公告)号：EP1265467A2

公开(公告)日：2002-12-11

申请号：EP02253946.4

申请日：2002-06-06

Applicant: NGK INSULATORS, LTD.

Inventor： Takeuchi, Yukihisa, I.P.D. NGK Insulators, Ltd. ,  Tsuji, Hiroyuki, I.P.D. NGK Insulators, Ltd. ,  Kitamura, Kazumasa, I.P.D. NGK Insulators, Ltd. ,  Yamaguchi, Yoshinori, I.P.D. NGK Insulators, Ltd.

IPC: H05K3/00 ,  H05K3/46 ,  B26F1/02

CPC classification number: B32B38/04 ,  B26F1/02 ,  B26F2210/08 ,  B32B2038/047 ,  B32B2457/08 ,  H05K3/005 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/4638 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/0195 ,  H05K2203/1476 ,  H05K2203/167

Abstract: A perforation of a multilayer board has a surface-profile precision of 8 µm or less, and the ratio of a diameter or the minimum distance between the opposing edges on the opening surface thereof to the axial length is preferably from about 1 : 1 to 1 : 15. The multilayer board is fabricated by a punching machine comprising a punch and a stripper such that a required number of plates are prepared, the first plate is perforated by the punch and is pulled up by closely attaching it to the stripper while leaving the punch in the first bore, the second plate is perforated by the punch and is pulled up together with the first plate while leaving the punch in the second bore, and subsequently, the following plates are perforated by the punch and the perforated plates are stacked along the punch serving as a stacking axis sequentially.

Abstract translation: 多层电路板的穿孔具有8微米或更小的表面轮廓精度，和一个直径或相对的边缘之间的开口在其表面上的轴向长度的最小距离的比为约1，优选为：1至 1：15的多层基板由冲压机，它包括一个冲头和一个汽提器搜索做准备板的所需数量的制造中，第一板由冲头穿孔，并且通过将其贴紧到汽提塔，同时留下拉升 在所述第一孔的冲头，第二板由冲头穿孔，并且同时使所述第二孔中的冲头与所述第一板一起拉起，随后，将下述板由冲头穿孔和穿孔板被堆叠 沿作为堆叠轴顺序地冲头。

公开(公告)号：EP1250033A2

公开(公告)日：2002-10-16

申请号：EP02013314.6

申请日：1997-12-23

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： Tsukamoto, Masahide

IPC: H05K3/40 ,  H05K3/46 ,  H05K3/20 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L24/80 ,  H01L23/3107 ,  H01L23/49827 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K1/115 ,  H05K3/007 ,  H05K3/20 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/462 ,  H05K3/4623 ,  H05K3/4658 ,  H05K2201/0367 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/0152 ,  H05K2203/1461 ,  Y10T29/49126 ,  Y10T29/49165 ,  Y10T29/49345 ,  H01L2924/00

Abstract: A printed circuit board has: a base material layer having a first via hole; and an insulating layer having a second via hole, the insulating layer being provided on one surface of the base material layer, wherein a cross-sectional area of the second via hole is smaller than a cross-sectional area of said first via hole, and wherein the first and second via holes are filled with a conductive material.