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31 条记录 (耗时 0.021 秒)

    DIELECTRIC LAYERS HAVING ORDERED ELONGATE PORES
    3.
    发明申请
    DIELECTRIC LAYERS HAVING ORDERED ELONGATE PORES 审中-公开
    具有订购的ELONGATE PORES的电介质层

    公开(公告)号：US20150170926A1

    公开(公告)日：2015-06-18

    申请号：US14108255

    申请日：2013-12-16

    申请人： David J. Michalak ,  Robert L. Bristol ,  Arkaprabha Sengupta ,  Mauro J. Kobrinsky

    发明人： David J. Michalak ,  Robert L. Bristol ,  Arkaprabha Sengupta ,  Mauro J. Kobrinsky

    IPC分类号： H01L21/308 ,  H01L23/50 ,  H01L21/311

    CPC分类号： H01L23/50 ,  H01L21/02203 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/7682 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  Y10T428/233 ,  Y10T428/249975 ,  H01L2924/00

    摘要： Embodiments of the present disclosure describe dielectric layers and methods for their fabrication and use. In some embodiments, a dielectric layer may include a dielectric material and a plurality of elongate pores. The dielectric material may have a first surface and an opposing second surface spaced away from the first surface in a direction defined by an axis, and may have a Young's modulus (E0) in the direction defined by the axis. Individual elongate pores of the plurality of elongate pores may extend from the second surface with a longitudinal axis substantially parallel to the axis. The plurality of elongate pores may provide the dielectric layer with a porosity, p, greater than approximately 30%, and the dielectric layer may have a Young's modulus approximately equal to E0*(1−p) in the direction defined by the axis. Other embodiments may be described and/or claimed.

    摘要翻译： 本公开的实施例描述了用于其制造和使用的电介质层及其方法。 在一些实施例中，电介质层可以包括电介质材料和多个细长孔。 电介质材料可以具有在由轴线限定的方向上与第一表面隔开的第一表面和相对的第二表面，并且可以在由轴限定的方向上具有杨氏模量（E0）。 多个细长孔中的单个细长孔可以从第二表面延伸，其纵轴基本上平行于该轴。 多个细长的孔可以提供介电层具有大于约30％的孔隙率p，并且电介质层可以具有在由轴限定的方向上大约等于E0 *（1-p）的杨氏模量。 可以描述和/或要求保护其他实施例。

    Optical waveguide structure
    4.
    发明授权
    Optical waveguide structure 有权
    光波导结构

    公开(公告)号：US09036954B2

    公开(公告)日：2015-05-19

    申请号：US13078210

    申请日：2011-04-01

    申请人： Mauro J. Kobrinsky ,  Bruce A. Block ,  Peter L. Chang

    发明人： Mauro J. Kobrinsky ,  Bruce A. Block ,  Peter L. Chang

    IPC分类号： G02F1/035 ,  G02F1/025 ,  G02F1/065 ,  G02F1/225

    CPC分类号： G02F1/035 ,  G02F1/025 ,  G02F1/065 ,  G02F1/225 ,  G02F2201/18

    摘要： Embodiments of the invention describe a multi-segment optical waveguide that enables an optical modulator to be low-power and athermal by decreasing the device length needed for a given waveguide length. Embodiments of the invention describe an optical waveguide that is folded onto itself, and thus includes at least two sections. Thus, embodiments of the invention may decrease the device size of a modulator by at least around a factor of two if the device is folded twofold (device size may be further reduced if the modulator is folded threefold, four-fold, five-fold, etc.).Embodiments of the invention further enable the electrode length required to create the desired electro-optic effect for the multi-segment optical waveguide to be reduced. In embodiments of the invention, certain electrodes may be “shared” amongst the different segments of the waveguide, thereby reducing the power requirement and capacitance of a device having a waveguide of a given length.

    摘要翻译： 本发明的实施例描述了一种多段光波导，其通过减小给定波导长度所需的器件长度，使光调制器能够实现低功率和无热性。 本发明的实施例描述了折叠到其自身上的光波导，因此包括至少两个部分。 因此，如果将器件折叠两倍，则本发明的实施例可以将调制器的器件尺寸减小至少约二分之一（如果调制器折叠三倍，四倍，五倍， 等等。）。 本发明的实施例还使得能够减少为多分段光波导产生期望的电光效应所需的电极长度。 在本发明的实施例中，某些电极可以在波导的不同部分之间“共享”，由此降低具有给定长度的波导的器件的功率需求和电容。

    POLING STRUCTURES AND METHODS FOR PHOTONIC DEVICES EMPLOYING ELECTRO-OPTICAL POLYMERS
    5.
    发明申请
    POLING STRUCTURES AND METHODS FOR PHOTONIC DEVICES EMPLOYING ELECTRO-OPTICAL POLYMERS 审中-公开
    使用电光聚合物的光电器件的结构和方法

    公开(公告)号：US20140086523A1

    公开(公告)日：2014-03-27

    申请号：US13629396

    申请日：2012-09-27

    申请人： Bruce A. BLOCK ,  Mauro J. KOBRINSKY ,  Miriam R. RESHOTKO ,  Shawna M. Liff

    发明人： Bruce A. BLOCK ,  Mauro J. KOBRINSKY ,  Miriam R. RESHOTKO ,  Shawna M. Liff

    IPC分类号： G02B6/26 ,  H05K13/00 ,  G02F1/035

    CPC分类号： G02F1/065 ,  G02F1/225 ,  G02F2201/126 ,  Y10T29/49002

    摘要： EOP-based photonic devices employing coplanar electrodes and in-plane poled chromophores and methods of their manufacture. In an individual EOP-based photonic device, enhanced performance is achieved through in-plane poled chromophores having opposing polarities, enabling, for example, a push-pull optical modulator with reduced operational voltage and switching power relative to a conventional MZ modulator. For a plurality of EOP-based photonic devices, enhanced manufacturability is achieved through a sacrificial interconnect enabling concurrent in-plane poling of many EOP regions disposed on a substrate.

    摘要翻译： 采用共面电极和面内极化发色团的基于EOP的光子器件及其制造方法。 在单个基于EOP的光子器件中，通过具有相反极性的面内极化发色团实现了增强的性能，使得例如相对于常规MZ调制器具有降低的操作电压和开关功率的推挽式光调制器。 对于多个基于EOP的光子器件，通过牺牲互连实现增强的可制造性，从而使得能够在布置在衬底上的许多EOP区域同时进行面内极化。

    Method of signal distribution based on a standing wave within a closed loop path
    6.
    发明授权
    Method of signal distribution based on a standing wave within a closed loop path 失效
    基于闭环路径内驻波的信号分配方法

    公开(公告)号：US07120817B2

    公开(公告)日：2006-10-10

    申请号：US10447706

    申请日：2003-05-29

    申请人： Mauro J. Kobrinsky ,  Sourav Chakravarty ,  R. Scott List

    发明人： Mauro J. Kobrinsky ,  Sourav Chakravarty ,  R. Scott List

    IPC分类号： G06F1/04

    CPC分类号： G06F1/10

    摘要： A closed-loop based timing signal distribution architecture includes at least one signal source coupled to a signal path disposed in a closed loop arrangement to facilitate generation of a standing wave signal within the signal path. In one embodiment, at least one receiver is coupled to the signal path to generate at least one digital clock signal based upon the standing wave signal.

    摘要翻译： 基于闭环的定时信号分配架构包括耦合到以闭环布置设置的信号路径的至少一个信号源，以便于在信号路径内产生驻波信号。 在一个实施例中，至少一个接收器耦合到信号路径，以基于驻波信号产生至少一个数字时钟信号。

    TECHNIQUES FOR ENHANCING FRACTURE RESISTANCE OF INTERCONNECTS
    9.
    发明申请
    TECHNIQUES FOR ENHANCING FRACTURE RESISTANCE OF INTERCONNECTS 有权
    提高互连电阻的技术

    公开(公告)号：US20140210098A1

    公开(公告)日：2014-07-31

    申请号：US13753245

    申请日：2013-01-29

    申请人： Christopher J. Jezewski ,  Mauro J. Kobrinsky ,  Daniel Pantuso ,  Siddharth B. Bhingarde ,  Michael P. O'Day

    发明人： Christopher J. Jezewski ,  Mauro J. Kobrinsky ,  Daniel Pantuso ,  Siddharth B. Bhingarde ,  Michael P. O'Day

    IPC分类号： H01L23/00

    CPC分类号： H01L23/562 ,  H01L23/293 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/535 ,  H01L23/5381 ,  H01L23/5386 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Techniques and structure are disclosed for enhancing fracture resistance of back-end interconnects and other such interconnect structures by increasing via density. Increased via density can be provided, for example, within the filler/dummified portion(s) of adjacent circuit layers within a die. In some cases, an electrically isolated (floating) filler line of an upper circuit layer may include a via which lands on a floating filler line of a lower circuit layer in a region corresponding to where the filler lines cross/intersect. In some such cases, the floating filler line of the upper circuit layer may be formed as a dual-damascene structure including such a via. In some embodiments, a via similarly may be provided between a floating filler line of the upper circuit layer and a sufficiently electrically isolated interconnect line of the lower circuit layer. The techniques/structure can be used to provide mechanical integrity for the die.

    摘要翻译： 公开了通过增加通孔密度来提高后端互连和其它这种互连结构的抗断裂性的技术和结构。 可以例如在模具内的相邻电路层的填充/加工部分内提供通孔密度的增加。 在一些情况下，上电路层的电隔离（浮置）填充线可以包括在对应于填充线交叉/相交的区域中的下电路层的浮动填充线上的通孔。 在一些这样的情况下，上电路层的浮动填充线可以形成为包括这种通孔的双镶嵌结构。 在一些实施例中，可以在上电路层的浮动填充线和下电路层的充分电隔离的互连线之间提供通孔。 技术/结构可用于为模具提供机械完整性。