公开(公告)号：US08563141B2

公开(公告)日：2013-10-22

申请号：US12716193

申请日：2010-03-02

Applicant: Jae Joon Lee ,  Jin Yong Ahn ,  Suk Hyeon Cho ,  Ki Hwan Kim ,  Seok Kyu Lee

Inventor： Jae Joon Lee ,  Jin Yong Ahn ,  Suk Hyeon Cho ,  Ki Hwan Kim ,  Seok Kyu Lee

IPC: B21C1/00

CPC classification number: H05K3/007 ,  B32B3/10 ,  B32B3/14 ,  B32B3/18 ,  B32B7/04 ,  B32B15/00 ,  B32B15/043 ,  B32B15/08 ,  B32B15/20 ,  B32B27/08 ,  B32B2457/08 ,  H05K3/0097 ,  H05K3/205 ,  H05K2201/0355 ,  Y10T156/10 ,  Y10T156/1052 ,  Y10T428/12 ,  Y10T428/12229 ,  Y10T428/12264 ,  Y10T428/12271 ,  Y10T428/161 ,  Y10T428/19 ,  Y10T428/192 ,  Y10T428/239 ,  Y10T428/24917

Abstract: Disclosed is a carrier for manufacturing a printed circuit board, which includes a first carrier including a first binder having a first opening and a first metal layer formed in the first opening of the first binder, and a second carrier, stacked with the first carrier and including a second binder having a second opening and a second metal layer which is formed in the second opening of the second binder and which partially overlaps with the first metal layer, so that the carrier is simply configured and the binders are formed not only on the lateral surfaces of the metal layers but also on the upper surfaces thereof, thus improving the reliability of bonding of the carrier at the periphery. A method of manufacturing the carrier and a method of manufacturing a printed circuit board using the carrier are also provided.

Abstract translation: 公开了一种用于制造印刷电路板的载体，其包括第一载体，其包括具有第一开口的第一粘合剂和形成在第一粘合剂的第一开口中的第一金属层，以及与第一载体堆叠的第二载体， 包括具有第二开口的第二粘合剂和形成在第二粘合剂的第二开口中并且与第一金属层部分重叠的第二金属层，使得载体被简单地构造，并且粘结剂不仅形成在 金属层的侧面，也在其上表面，从而提高载体在周边的接合的可靠性。 还提供了制造载体的方法和使用该载体制造印刷电路板的方法。

公开(公告)号：US20110067901A1

公开(公告)日：2011-03-24

申请号：US12614411

申请日：2009-11-07

Applicant: Jin Ho KIM ,  Seok Kyu LEE ,  Jae Joon LEE ,  Sung Won JEONG

Inventor： Jin Ho KIM ,  Seok Kyu LEE ,  Jae Joon LEE ,  Sung Won JEONG

IPC: H05K1/00

CPC classification number: H05K1/0271 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K1/0224 ,  H05K1/141 ,  H05K3/4682 ,  H05K2201/049 ,  H05K2201/09136 ,  H05K2201/09681 ,  H01L2924/00

Abstract: Disclosed is a package substrate, in which the plating area of a first plating layer formed on a layer which is to be connected to a motherboard is larger than the plating area of a second plating layer formed on a layer which is to be connected to an electronic part, and open portions are formed on the first plating layer, thus balancing the plating areas of the plating layers formed on the layers of the package substrate, thereby minimizing warpage of the package substrate due to differing coefficients of thermal expansion.

Abstract translation: 公开了一种封装基板，其中形成在要连接到母板的层上的第一镀层的电镀面积大于形成在要连接到母板的层上的第二镀层的镀覆面积 电子部分和开口部分形成在第一镀层上，从而平衡形成在封装衬底的层上的镀层的电镀区域，由此由于不同的热膨胀系数使封装衬底的翘曲最小化。

公开(公告)号：US20100096177A1

公开(公告)日：2010-04-22

申请号：US12320284

申请日：2009-01-22

Applicant: Seok Kyu Lee ,  Soon OH Jung ,  Jong Kuk Hong ,  Soon Jin Cho

Inventor： Seok Kyu Lee ,  Soon OH Jung ,  Jong Kuk Hong ,  Soon Jin Cho

IPC: H05K1/11 ,  H05K3/42

CPC classification number: H05K3/00 ,  H05K1/113 ,  H05K3/0052 ,  H05K3/007 ,  H05K3/4007 ,  H05K3/426 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2203/0156 ,  H05K2203/054 ,  H05K2203/1572

Abstract: Disclosed herein is a coreless substrate having filled via pads and a method of manufacturing the same. Insulating layers are formed on both sides of a build-up layer, and via-pads are embedded in the insulating layers such that the via-pads are flush with the insulating layers. The via pads are not separated from a substrate, and thus reliability of the pads is increased. Flatness of bumps is increased, and thus bonding of flip chips becomes easy.

Abstract translation: 本文公开了具有填充通孔焊盘的无芯基板及其制造方法。 绝缘层形成在堆积层的两侧，并且通孔焊盘嵌入在绝缘层中，使得通孔焊盘与绝缘层齐平。 通孔焊盘不与衬底分离，因此焊盘的可靠性增加。 凸起的平坦度增加，因此倒装芯片的结合变得容易。

公开(公告)号：US20100096171A1

公开(公告)日：2010-04-22

申请号：US12320366

申请日：2009-01-23

Applicant: Seok Kyu Lee ,  Jae Joon Lee ,  Ki Hwan Kim

Inventor： Seok Kyu Lee ,  Jae Joon Lee ,  Ki Hwan Kim

IPC: H05K1/09 ,  B32B38/10 ,  H05K1/11

CPC classification number: H05K3/3484 ,  H05K3/244 ,  H05K3/282 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/09472 ,  H05K2201/09481 ,  H05K2203/0152 ,  H05K2203/0338 ,  H05K2203/043

Abstract: Disclosed herein is a printed circuit board having round solder bumps and a method of manufacturing the same. The solder bump is configured to have a round connecting surface in contact with a pad, and thus have an increased contact area with respect to the pad, thus improving connection reliability. The solder bumps have uniform heights.

Abstract translation: 这里公开了具有圆形焊料凸块的印刷电路板及其制造方法。 焊料凸块被构造成具有与焊盘接触的圆形连接表面，因此相对于焊盘具有增加的接触面积，从而提高连接可靠性。 焊料凸点具有均匀的高度。

公开(公告)号：US07570491B2

公开(公告)日：2009-08-04

申请号：US10728591

申请日：2003-12-04

Applicant: Seok-Kyu Lee ,  Byoung-Youl Min ,  Chang-Hyun Nam ,  Hyun-Ju Jin ,  Jang-Kyu Kang

Inventor： Seok-Kyu Lee ,  Byoung-Youl Min ,  Chang-Hyun Nam ,  Hyun-Ju Jin ,  Jang-Kyu Kang

IPC: H05K1/02 ,  H05K1/16

CPC classification number: H05K1/162 ,  H05K3/4652 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/0355 ,  H05K2201/0358 ,  H05K2201/09509 ,  H05K2203/1461

Abstract: Disclosed herein is a printed circuit board with embedded capacitors therein which comprises inner via holes filled with a high dielectric polymer capacitor paste composed of a composite of BaTiO3 and an epoxy resin, and a process for manufacturing the printed circuit board.

Abstract translation: 这里公开了一种其中具有嵌入式电容器的印刷电路板，其包括填充有由BaTiO 3和环氧树脂的复合材料组成的高介电聚合物电容器糊的内部通孔，以及用于制造印刷电路板的工艺。

公开(公告)号：US20080125456A1

公开(公告)日：2008-05-29

申请号：US11718547

申请日：2005-11-11

Applicant: Sang Joon Lee ,  Hee Jong Shin ,  Seok Kyu Lee ,  Ji Hun Yun

Inventor： Sang Joon Lee ,  Hee Jong Shin ,  Seok Kyu Lee ,  Ji Hun Yun

IPC: A61K31/436

CPC classification number: A61K47/10 ,  A61K9/0019 ,  A61K9/08 ,  A61K47/14

Abstract: This invention relates to tacrolimus injection comprising tacrolimus as an active ingredient, macrogol 15 hydroxystearate as a surfactant and a non-aqueous solvent.

Abstract translation: 本发明涉及他克莫司注射剂，其包含他克莫司作为活性成分，羟基硬脂酸羟肟酸锌15作为表面活性剂和非水溶剂。

公开(公告)号：US20060014327A1

公开(公告)日：2006-01-19

申请号：US10976732

申请日：2004-10-29

Applicant: Suk-Hyeon Cho ,  Seok-Kyu Lee ,  Jong-Kuk Hong ,  Ho-Sik Jun ,  Jin-Soo Jeong ,  Chang-Sup Ryu ,  Jin-Yong Ahn

Inventor： Suk-Hyeon Cho ,  Seok-Kyu Lee ,  Jong-Kuk Hong ,  Ho-Sik Jun ,  Jin-Soo Jeong ,  Chang-Sup Ryu ,  Jin-Yong Ahn

IPC: H01L21/50

CPC classification number: H05K1/186 ,  H01L2224/82039 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H05K1/023 ,  H05K1/185 ,  H05K3/4614 ,  H05K3/4652 ,  H05K2201/10636 ,  H05K2203/1189 ,  Y02P70/611

Abstract: Disclosed is a method of fabricating a PCB including an embedded passive chip, in which the passive chip is mounted on the PCB and an insulator is then laminated on the PCB, or in which a blind hole for receiving the passive chip is formed in the PCB and the passive chip is mounted in the blind hole.

Abstract translation: 公开了一种制造包括嵌入式无源芯片的PCB的方法，其中无源芯片安装在PCB上，然后将绝缘体层合在PCB上，或者在PCB中形成用于接收无源芯片的盲孔 无源芯片安装在盲孔中。

公开(公告)号：US20050199681A1

公开(公告)日：2005-09-15

申请号：US11117315

申请日：2005-04-29

Applicant: Seok-Kyu Lee ,  Jang-Kyu Kang ,  Hyun-Ju Jin ,  Byoung-Youl Min

Inventor： Seok-Kyu Lee ,  Jang-Kyu Kang ,  Hyun-Ju Jin ,  Byoung-Youl Min

IPC: H05K3/46 ,  H05K1/16 ,  H05K3/00 ,  H05K3/42 ,  B23K1/00

CPC classification number: H05K1/162 ,  H05K3/0023 ,  H05K3/429 ,  H05K3/4652 ,  H05K3/4661 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2203/0568 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49155

Abstract: Disclosed herein are a printed circuit board with embedded capacitors therein and a process for manufacturing the printed circuit board. The embedded capacitors are formed by applying a photosensitive insulating resin to a printed circuit board inner layer, and applying a high dielectric polymer capacitor paste thereto.

Abstract translation: 这里公开了一种其中具有嵌入式电容器的印刷电路板和用于制造印刷电路板的工艺。 嵌入式电容器通过将印刷电路板内层施加感光绝缘树脂，并向其施加高介电聚合物电容器膏而形成。

公开(公告)号：US08445790B2

公开(公告)日：2013-05-21

申请号：US12320284

申请日：2009-01-22

Applicant: Seok Kyu Lee ,  Soon Oh Jung ,  Jong Kuk Hong ,  Soon Jin Cho

Inventor： Seok Kyu Lee ,  Soon Oh Jung ,  Jong Kuk Hong ,  Soon Jin Cho

IPC: H05K1/11

CPC classification number: H05K3/00 ,  H05K1/113 ,  H05K3/0052 ,  H05K3/007 ,  H05K3/4007 ,  H05K3/426 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2203/0156 ,  H05K2203/054 ,  H05K2203/1572

Abstract: Disclosed herein is a coreless substrate having filled via pads and a method of manufacturing the same. Insulating layers are formed on both sides of a build-up layer, and via-pads are embedded in the insulating layers such that the via-pads are flush with the insulating layers. The via pads are not separated from a substrate, and thus reliability of the pads is increased. Flatness of bumps is increased, and thus bonding of flip chips becomes easy.

Abstract translation: 本文公开了具有填充通孔焊盘的无芯基板及其制造方法。 绝缘层形成在堆积层的两侧，并且通孔焊盘嵌入在绝缘层中，使得通孔焊盘与绝缘层齐平。 通孔焊盘不与衬底分离，因此焊盘的可靠性增加。 凸起的平坦度增加，因此倒装芯片的结合变得容易。

公开(公告)号：US20110076472A1

公开(公告)日：2011-03-31

申请号：US12655516

申请日：2009-12-30

Applicant: Jin Ho Kim ,  Seok Kyu Lee ,  Jae Joon Lee ,  Sung Won Jeong

Inventor： Jin Ho Kim ,  Seok Kyu Lee ,  Jae Joon Lee ,  Sung Won Jeong

IPC: B32B7/02

CPC classification number: H05K3/4682 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K1/0271 ,  H05K2201/0352 ,  H05K2201/068 ,  Y10T428/2495 ,  H01L2924/00

Abstract: Disclosed is a package substrate, in which the plating area of a first plating layer formed on a layer which is to be connected to a motherboard is larger than the plating area of a second plating layer formed on a layer which is to be connected to an electronic part, and the plating thickness of the second plating layer is greater than the plating thickness of the first plating layer, thus balancing the plating volumes of the plating layers formed on the layers of the package substrate, thereby minimizing warpage of the package substrate which results from the coefficients of thermal expansion being different.

Abstract translation: 公开了一种封装基板，其中形成在要连接到母板的层上的第一镀层的电镀面积大于形成在要连接到母板的层上的第二镀层的镀覆面积 电子部分，并且第二镀层的镀层厚度大于第一镀层的镀层厚度，从而平衡形成在包装衬底的层上的镀层的镀层体积，从而最小化封装衬底的翘曲 来自热膨胀系数的结果不同。