公开(公告)号：US20240304450A1

公开(公告)日：2024-09-12

申请号：US18118736

申请日：2023-03-07

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： An-Hsuan HSU ,  Chin-Li KAO

IPC: H01L21/285 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/46 ,  H05K1/02

CPC classification number: H01L21/28506 ,  H01L21/4889 ,  H01L21/56 ,  H01L23/46 ,  H01L24/20 ,  H05K1/0296

Abstract: An electronic package structure includes a first electronic component, a first thermal conductive structure and a second thermal conductive structure. The first thermal conductive structure is disposed over the first electronic component. The second thermal conductive structure is disposed between the first electronic component and the first thermal conductive structure. A first heat transfer rate of the second thermal conductive structure along a first direction from the first electronic component to the first thermal conductive structure is greater than a second heat transfer rate of the second thermal conductive structure along a second direction nonparallel with the first direction from the first electronic component to an element other than the first thermal conductive structure.

公开(公告)号：US20220384381A1

公开(公告)日：2022-12-01

申请号：US17334622

申请日：2021-05-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chung-Hung LAI ,  Chin-Li KAO ,  Chih-Yi HUANG ,  Teck-Chong LEE

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L23/14 ,  H01L25/065

Abstract: An electronic device package is provided. The electronic device package includes a redistribution layer (RDL), a first electronic component and an interconnector. The RDL includes a topmost circuit layer, and the topmost circuit layer includes a conductive trace. The first electronic component is disposed over the RDL. The interconnector is disposed between the RDL and the first electronic component. A direction is defined by extending from a center of the first electronic component toward an edge of the first electronic component, and the direction penetrates a first sidewall and a second sidewall of the interconnector, the second sidewall is farther from the center of the first electronic component than the first sidewall is, and the conductive trace is outside a projection region of the second sidewall.

公开(公告)号：US20210272866A1

公开(公告)日：2021-09-02

申请号：US17322767

申请日：2021-05-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ya-Yu HSIEH ,  Chin-Li KAO ,  Chung-Hsuan TSAI ,  Chia-Pin CHEN

IPC: H01L23/29 ,  H01L23/00 ,  H01L23/31 ,  H01L21/66

Abstract: The present disclosure provides a semiconductor package structure having a semiconductor die having an active surface, a conductive bump on the active surface, configured to electrically couple the semiconductor die to an external circuit, the conductive bump having a bump height, a dielectric encapsulating the semiconductor die and the conductive bump, and a plurality of fillers in the dielectric, each of the fillers comprising a diameter, wherein a maximum diameter of the fillers is smaller than the bump height.

公开(公告)号：US20240063159A1

公开(公告)日：2024-02-22

申请号：US17891949

申请日：2022-08-19

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： An-Hsuan HSU ,  Chin-Li KAO

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L24/08 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0657 ,  H01L23/49811 ,  H01L23/49838 ,  H01L2924/35121 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06589 ,  H01L2224/08145 ,  H01L2224/32145 ,  H01L2224/32221 ,  H01L2224/08221 ,  H01L2224/80098 ,  H01L2224/80895 ,  H01L2224/83098 ,  H01L2224/05541 ,  H01L2224/05556 ,  H01L2224/08503 ,  H01L2224/05647 ,  H01L2224/05605 ,  H01L2224/80815

Abstract: A package structure is disclosed. The package structure includes a substrate including a conductive element and a plurality of wires having a surface area through which heat of the conductive element can be dissipated, lowering a bonding temperature of the conductive element. The package structure also includes a conductive layer disposed between the conductive element of the substrate and the plurality of wires. The conductive contact layer attaches the plurality of wires over the conductive element.

公开(公告)号：US20230268314A1

公开(公告)日：2023-08-24

申请号：US17676094

申请日：2022-02-18

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Shan-Bo WANG ,  Chin-Li KAO ,  An-Hsuan HSU

IPC: H01L23/00 ,  H01L25/10

CPC classification number: H01L24/81 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L25/105 ,  H01L23/49816 ,  H01L2224/11849 ,  H01L2224/14505 ,  H01L2224/17505 ,  H01L2224/81097 ,  H01L2224/81211 ,  H01L2224/81815 ,  H01L2224/81825 ,  H01L2224/81935 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: A semiconductor device package and a fabrication method thereof are disclosed. The semiconductor package comprises: a package component having a first mounting surface and a second mounting surface; and a first electronic component having a first conductive pad signal communicatively mounted on the first mounting surface through a first type connector; wherein the first type connector comprises a first solder composition having a lower melting point layer sandwiched between a pair of higher melting point layers, wherein the lower melting point layer is composed of alloys capable of forming a room temperature eutectic.

公开(公告)号：US20210287999A1

公开(公告)日：2021-09-16

申请号：US16817407

申请日：2020-03-12

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Fan-Yu MIN ,  Chen-Hung LEE ,  Wei-Hang TAI ,  Yuan-Tzuo LUO ,  Wen-Yuan CHUANG ,  Chun-Cheng KUO ,  Chin-Li KAO

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

Abstract: A package structure and a manufacturing method are provided. The package structure includes a wiring structure, a first electronic device and a second electronic device. The first electronic device is disposed on the wiring structure. The second electronic device is disposed on the wiring structure. The first electronic device and the second electronic device are disposed side by side. A gap between the first electronic device and the second electronic device is greater than or equal to about 150 μm.

公开(公告)号：US20210257331A1

公开(公告)日：2021-08-19

申请号：US16793991

申请日：2020-02-18

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yun-Ching HUNG ,  Yung-Sheng LIN ,  Chin-Li KAO

IPC: H01L23/00

Abstract: Present disclosure provides a semiconductor package, including a first substrate having a first active surface and a first trench recessed from the first active surface, a second substrate having a second trench facing the first trench, and a pathway cavity defined by the first trench and the second trench. The first trench comprises a first metal protrusion and a first insulating protrusion. A method for manufacturing the semiconductor package described herein is also disclosed.

公开(公告)号：US20190074264A1

公开(公告)日：2019-03-07

申请号：US15698451

申请日：2017-09-07

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Bo-Syun CHEN ,  Tang-Yuan CHEN ,  Yu-Chang CHEN ,  Jin-Feng YANG ,  Chin-Li KAO ,  Meng-Kai SHIH

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/13 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/29347 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/83192 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06537 ,  H01L2225/06558 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2224/81

Abstract: A semiconductor package structure includes a first substrate, at least one first semiconductor element and a second substrate. The first semiconductor element is attached to the first substrate. The second substrate defines a cavity and includes a plurality of thermal vias. One end of each of the thermal vias is exposed in the cavity, and the first semiconductor element is disposed within the cavity and thermally connected to the thermal vias.

公开(公告)号：US20250038078A1

公开(公告)日：2025-01-30

申请号：US18227892

申请日：2023-07-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： An-Hsuan HSU ,  Chin-Li KAO

IPC: H01L23/498

Abstract: A bonding structure and a package structure are provided. The bonding structure includes a first pad and a plurality of first wires. The first pad has a top surface including a first region and a second region, wherein the second region is closer to an edge of the top surface of the first pad than the first region is. The first wires are on the top surface of the first pad, wherein a number of the first wires on the first region is greater than a number of the first wires on the second region.

公开(公告)号：US20190287947A1

公开(公告)日：2019-09-19

申请号：US16434008

申请日：2019-06-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Bo-Syun CHEN ,  Tang-Yuan CHEN ,  Yu-Chang CHEN ,  Jin-Feng YANG ,  Chin-Li KAO ,  Meng-Kai SHIH

IPC: H01L25/065 ,  H01L23/552 ,  H01L25/00 ,  H01L23/13 ,  H01L23/498 ,  H01L21/48 ,  H01L23/367 ,  H01L23/538

Abstract: A semiconductor package structure includes: (1) a first substrate; (2) at least one first semiconductor element attached to the first substrate; and (3) a second substrate including a plurality of thermal vias and a plurality of conductive vias, wherein one end of each of the thermal vias directly contacts the first semiconductor element.