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    Method for plasma etching a microelectronic topography using a pulse bias power
    1.
    发明授权
    Method for plasma etching a microelectronic topography using a pulse bias power 有权
    使用脉冲偏置功率等离子体蚀刻微电子拓扑的方法

    公开(公告)号：US06759339B1

    公开(公告)日：2004-07-06

    申请号：US10319318

    申请日：2002-12-13

    申请人： Chang Ju Choi ,  Benjamin Schwarz

    发明人： Chang Ju Choi ,  Benjamin Schwarz

    IPC分类号： H01L21302

    CPC分类号： B82Y10/00 ,  H01L21/32136 ,  H01L43/12

    摘要： A method is provided which includes pulsing power applied to a microelectronic topography between a high level and a low level during a plasma etch process. In particular, the high level may be sufficient to form etch byproducts at a faster rate than a rate of removal of the etch byproducts from the reaction chamber at the high level. In contrast, the low level may be sufficient to form etch byproducts at a rate that is less than a rate of removal of the etch byproducts at the low level. In this manner, an etched topography may be formed without an accumulation of residue upon its periphery. Such a method may be particularly beneficial in an embodiment in which the etch byproducts include a plurality of nonvolatile compounds, such as in the fabrication of a magnetic junction of an MRAM device, for example.

    摘要翻译： 提供了一种方法，其包括在等离子体蚀刻工艺期间施加到高电平和低电平之间的微电子拓扑的脉冲功率。 特别地，高水平可能足以以比以高水平从反应室去除蚀刻副产物的速率更快的速率形成蚀刻副产物。 相比之下，低水平可能足以以低于在低水平下去除蚀刻副产物的速率形成蚀刻副产物。 以这种方式，可以形成蚀刻的形貌，而不会在其周边上积聚残留物。 这种方法在其中蚀刻副产物包括多种非挥发性化合物的实施方案中可能是特别有利的，例如在制造MRAM器件的磁结时。

    Methods for processing substrates in process systems having shared resources
    5.
    发明授权
    Methods for processing substrates in process systems having shared resources 有权
    在具有共享资源的处理系统中处理衬底的方法

    公开(公告)号：US08496756B2

    公开(公告)日：2013-07-30

    申请号：US12915240

    申请日：2010-10-29

    申请人： James P. Cruse ,  Dermot Cantwell ,  Ming Xu ,  Charles Hardy ,  Benjamin Schwarz ,  Kenneth S. Collins ,  Andrew Nguyen ,  Zhifeng Sui ,  Evans Lee

    发明人： James P. Cruse ,  Dermot Cantwell ,  Ming Xu ,  Charles Hardy ,  Benjamin Schwarz ,  Kenneth S. Collins ,  Andrew Nguyen ,  Zhifeng Sui ,  Evans Lee

    IPC分类号： B08B6/00

    CPC分类号： H01L21/6719 ,  H01J37/32899

    摘要： Methods for processing substrates in twin chamber processing systems having first and second process chambers and shared processing resources are provided herein. In some embodiments, a method may include flowing a process gas from a shared gas panel to a processing volume of the first process chamber and to a processing volume of the second process chamber; forming a first plasma in the first processing volume to process the first substrate and a second plasma to process the second substrate; monitoring the first processing volume and the second processing volume to determine if a process endpoint is reached in either volume; and either terminating the first and second plasma simultaneously when a first endpoint is reached; or terminating the first plasma when a first endpoint is reached in the first processing volume while continuing to provide the second plasma in the second processing volume until a second endpoint is reached.

    摘要翻译： 本文提供了具有第一处理室和第二处理室以及共享处理资源的双室处理系统中处理基板的方法。 在一些实施例中，一种方法可以包括将处理气体从共用气体面板流动到第一处理室的处理容积和第二处理室的处理容积; 在所述第一处理体积中形成第一等离子体以处理所述第一基板和第二等离子体以处理所述第二基板; 监测第一处理量和第二处理量以确定任一体积中是否达到过程终点; 并且当达到第一端点时同时终止第一和第二等离子体; 或在第一处理容积中达到第一端点时终止第一等离子体，同时继续在第二处理容积中提供第二等离子体直到达到第二端点。

    Gate etch process
    6.
    发明授权
    Gate etch process 有权
    门蚀刻工艺

    公开(公告)号：US07112834B1

    公开(公告)日：2006-09-26

    申请号：US10791657

    申请日：2004-03-02

    申请人： Benjamin Schwarz ,  Chan-Lon Yang ,  Kiyoko Ikeuchi ,  Peter Keswick ,  Lien Lee

    发明人： Benjamin Schwarz ,  Chan-Lon Yang ,  Kiyoko Ikeuchi ,  Peter Keswick ,  Lien Lee

    IPC分类号： H01L29/76

    CPC分类号： H01L21/31116 ,  H01L21/32137 ,  Y10S438/952

    摘要： A method of making a semiconductor structure includes etching an anti-reflective coating layer at a pressure of 10 millitorr or less; etching a nitride layer with a first nitride etch plasma having a first F:C ratio; and etching the nitride layer with a second nitride etch plasma having a second F:C ratio. The first F:C ratio is greater than the second F:C ratio.

    摘要翻译： 制造半导体结构的方法包括在10毫托或更低的压力下蚀刻抗反射涂层; 用具有第一F：C比率的第一氮化物蚀刻等离子体蚀刻氮化物层; 并用具有第二F：C比率的第二氮化物蚀刻等离子体蚀刻氮化物层。 第一F：C比大于第二F：C比。

    METHOD OF PATTERNING OF MAGNETIC TUNNEL JUNCTIONS
    7.
    发明申请
    METHOD OF PATTERNING OF MAGNETIC TUNNEL JUNCTIONS 失效
    电磁隧道结构的方法

    公开(公告)号：US20120276657A1

    公开(公告)日：2012-11-01

    申请号：US13095736

    申请日：2011-04-27

    申请人： Olivier Joubert ,  Benjamin Schwarz ,  Jérémy Gilbert Maurice Pereira ,  Kevin Menguelti ,  Erwine Maude Pargon ,  Maxime Darnon

    发明人： Olivier Joubert ,  Benjamin Schwarz ,  Jérémy Gilbert Maurice Pereira ,  Kevin Menguelti ,  Erwine Maude Pargon ,  Maxime Darnon

    IPC分类号： H01L21/8246

    CPC分类号： H01L43/12

    摘要： Embodiments of the invention generally relate to methods for fabricating devices on semiconductor substrates. More specifically, embodiments of the invention relate to methods of patterning magnetic materials. Certain embodiments described herein use a reducing chemistry containing a hydrogen gas or hydrogen containing gas with an optional dilution gas at temperatures ranging from 20 to 300 degrees Celsius at a substrate bias less than 1,000 DC voltage to reduce the amount of sputtering and redeposition. Exemplary hydrogen containing gases which may be used with the embodiments described herein include NH3, H2, CH4, C2H4, SiH4, and H2S. It has been found that patterning a magnetic tunnel junction with an oxidizer-free gas mixture comprising hydrogen maintains the integrity of the magnetic tunnel junction without producing harmful conductive residue.

    摘要翻译： 本发明的实施例一般涉及在半导体衬底上制造器件的方法。 更具体地，本发明的实施例涉及图案化磁性材料的方法。 本文所述的某些实施方案使用含有氢气或含氢气体的还原化学物质，其具有任选的稀释气体，温度范围为20-300摄氏度，衬底偏压小于1,000直流电压，以减少溅射和再沉积的量。 可与本文所述实施方案一起使用的示例性含氢气体包括NH 3，H 2，CH 4，C 2 H 4，SiH 4和H 2 S. 已经发现，使用包含氢的无氧化剂气体混合物构图磁隧道结保持了磁性隧道结的完整性，而不会产生有害的导电残留物。