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    Nickel alloy plated structure
    6.
    发明授权
    Nickel alloy plated structure 失效
    镍合金镀层结构

    公开(公告)号：US07472650B2

    公开(公告)日：2009-01-06

    申请号：US11865170

    申请日：2007-10-01

    申请人： Harry David Cox ,  Hsichang Liu ,  Nike Oluwakemi Medahunsi ,  Krystyna Waleria Semkow

    发明人： Harry David Cox ,  Hsichang Liu ,  Nike Oluwakemi Medahunsi ,  Krystyna Waleria Semkow

    IPC分类号： B05C17/06 ,  B32B3/24 ,  B32B15/20

    CPC分类号： C25D5/022 ,  C23C28/021 ,  C23C28/023 ,  C25D5/10 ,  H01L21/4867 ,  H05K3/1225 ,  H05K3/245 ,  H05K2201/09736 ,  Y10T428/12063 ,  Y10T428/12361 ,  Y10T428/12486 ,  Y10T428/1291

    摘要： A structure. The structure includes a layered configuration including a copper layer, a first layer, and a second layer. The first and second layers are disposed on opposite sides of the copper layer and are in direct mechanical contact with the copper layer. The first and second layers each include a same alloy of nickel and a metal consisting of cobalt, iron, copper, manganese, or molybdenum. A first region in the first layer extends completely through the first layer. A second region in the second layer extends completely through the second layer. A third region in the first layer extends completely through the first layer. The third region does not extend into any portion of the second layer. The first, second region, and third regions each include a photoresist or an opening such that photoresist or opening extends completely through the first, second, and first layer, respectively.

    摘要翻译： 一个结构。 该结构包括包括铜层，第一层和第二层的层状构造。 第一层和第二层设置在铜层的相对侧上，并与铜层直接机械接触。 第一层和第二层各自包括镍和由钴，铁，铜，锰或钼组成的金属的相同合金。 第一层中的第一区域完全延伸穿过第一层。 第二层中的第二区域完全延伸穿过第二层。 第一层中的第三区域完全延伸穿过第一层。 第三区域不延伸到第二层的任何部分。 第一，第二区域和第三区域各自包括光致抗蚀剂或开口，使得光致抗蚀剂或开口分别完全延伸穿过第一层，第二层和第一层。

    Partial wafer bonding and dicing
    8.
    发明授权
    Partial wafer bonding and dicing 失效
    部分晶片接合和切割

    公开(公告)号：US07078320B2

    公开(公告)日：2006-07-18

    申请号：US10710880

    申请日：2004-08-10

    申请人： Louis C. Hsu ,  Hsichang Liu ,  James R. Salimeno, III

    发明人： Louis C. Hsu ,  Hsichang Liu ,  James R. Salimeno, III

    IPC分类号： H01L21/326 ,  H01L21/46

    CPC分类号： H01L21/2007 ,  H01L21/78 ,  Y10S438/977

    摘要： Disclosed is a method of manufacturing integrated circuit chips that partially joins an integrated circuit wafer to a supporting wafer at a limited number of joining points. Once joined, the integrated circuit wafer is chemically-mechanically polished to reduce the thickness of the integrated circuit wafer. Then, after reducing the thickness of the integrated circuit wafer, the invention performs conventional processing on the integrated circuit wafer to form devices and wiring in the integrated circuit wafer. Next, the invention cuts through the integrated circuit wafer and the supporting wafer to form chip sections. During this cutting process, the integrated circuit wafer separates from the supporting wafer in chip sections where the integrated circuit wafer is not joined to the supporting wafer by the joining points. Chip sections where the integrated circuit wafer remains joined to the supporting wafer are thicker than the chips sections where the integrated circuit wafer separates from the supporting wafer.

    摘要翻译： 公开了一种制造在有限数量的接合点部分地将集成电路晶片连接到支撑晶片的集成电路芯片的方法。 一旦接合，集成电路晶片被化学机械抛光以减小集成电路晶片的厚度。 然后，在减小集成电路晶片的厚度之后，本发明对集成电路晶片进行常规处理，以在集成电路晶片中形成器件和布线。 接下来，本发明切割集成电路晶片和支撑晶片以形成芯片部分。 在该切割过程中，集成电路晶片与集成电路晶片通过接合点未接合到支撑晶片的芯片部分中的支撑晶片分离。 集成电路晶片保持接合到支撑晶片的芯片部分比集成电路晶片与支撑晶片分离的芯片部分更厚。

    PARTIAL WAFER BONDING AND DICING
    10.
    发明申请
    PARTIAL WAFER BONDING AND DICING 失效
    部分波形结合和定位

    公开(公告)号：US20060035443A1

    公开(公告)日：2006-02-16

    申请号：US10710880

    申请日：2004-08-10

    申请人： Louis Hsu ,  Hsichang Liu ,  James Salimeno III

    发明人： Louis Hsu ,  Hsichang Liu ,  James Salimeno III

    IPC分类号： H01L21/78 ,  H01L21/301 ,  H01L21/46

    CPC分类号： H01L21/2007 ,  H01L21/78 ,  Y10S438/977

    摘要： Disclosed is a method of manufacturing integrated circuit chips that partially joins an integrated circuit wafer to a supporting wafer at a limited number of joining points. Once joined, the integrated circuit wafer is chemically-mechanically polished to reduce the thickness of the integrated circuit wafer. Then, after reducing the thickness of the integrated circuit wafer, the invention performs conventional processing on the integrated circuit wafer to form devices and wiring in the integrated circuit wafer. Next, the invention cuts through the integrated circuit wafer and the supporting wafer to form chip sections. During this cutting process, the integrated circuit wafer separates from the supporting wafer in chip sections where the integrated circuit wafer is not joined to the supporting wafer by the joining points. Chip sections where the integrated circuit wafer remains joined to the supporting wafer are thicker than the chips sections where the integrated circuit wafer separates from the supporting wafer.

    摘要翻译： 公开了一种制造在有限数量的接合点部分地将集成电路晶片连接到支撑晶片的集成电路芯片的方法。 一旦接合，集成电路晶片被化学机械抛光以减小集成电路晶片的厚度。 然后，在减小集成电路晶片的厚度之后，本发明对集成电路晶片进行常规处理，以在集成电路晶片中形成器件和布线。 接下来，本发明切割集成电路晶片和支撑晶片以形成芯片部分。 在该切割过程中，集成电路晶片与集成电路晶片通过接合点未接合到支撑晶片的芯片部分中的支撑晶片分离。 集成电路晶片保持接合到支撑晶片的芯片部分比集成电路晶片与支撑晶片分离的芯片部分更厚。