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1.发明申请公开(公告)号：US20150023377A1
公开(公告)日：2015-01-22
申请号：US14510654
申请日：2014-10-09
Applicant: Cisco Technology, Inc.
Inventor： Kalpendu SHASTRI , Soham PATHAK , Vipulkumar PATEL , Bipin DAMA , Kishor DESAI
CPC classification number: H01S5/02415 , G02B6/42 , G02B6/4273 , H01S5/005 , H01S5/0064 , H01S5/02248 , H01S5/024 , H01S5/02469 , H01S5/4025
Abstract: An interposer (support substrate) for an opto-electronic assembly is formed to include a thermally-isolated region where temperature-sensitive devices (such as, for example, laser diodes) may be positioned and operate independent of temperature fluctuations in other areas of the assembly. The thermal isolation is achieved by forming a boundary of dielectric material through the thickness of the interposer, the periphery of the dielectric defining the boundary between the thermally isolated region and the remainder of the assembly. A thermo-electric cooler can be used in conjunction with the temperature-sensitive device(s) to stabilize the operation of these devices.
Abstract translation: 形成用于光电组件的插入器（支撑衬底），以包括热隔离区域，其中可以将温度敏感器件（例如激光二极管）定位并独立于其中的温度波动 部件。 通过形成介电材料的边界通过插入件的厚度来实现热隔离，绝缘体的外围限定了热隔离区域和组件的其余部分之间的边界。 热电冷却器可与温度敏感设备结合使用，以稳定这些设备的运行。
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Patent Agency Ranking
2.发明申请公开(公告)号：US20160109668A1
公开(公告)日：2016-04-21
申请号：US14517477
申请日：2014-10-17
Applicant: Cisco Technology, Inc.
Inventor： Stefan Martin PFNUER , Matthew Joseph TRAVERSO , Bipin DAMA
CPC classification number: G02B6/4257 , G02B6/4204 , G02B6/4232 , G02B6/428 , G02F1/011 , H05K1/181 , H05K1/182 , H05K2201/09063 , H05K2201/10121 , H05K2201/10446 , H05K2201/1053
Abstract: An optical transmitter may include a chip stack that includes an electrical IC that is mounted using solder balls to a photonic chip. These solder connections permit the electrical IC and the photonic chip to communicate. In addition, the transmitter may include a PCB coupled to the stack so that electrical signals in the PCB are transmitted to the IC and photonic chip (and vice versa). Instead of coupling the PCB to the stack using wire bonds attached to pads on a surface of the photonic chip, at least a portion of the PCB is disposed between the photonic chip and electrical IC. The PCB may also include bond pads used to form a direct solder connection to the electrical IC. As such, the electrical IC may include direct solder connections to both the PCB and the photonic chip.
Abstract translation: 光发射机可以包括芯片堆叠，其包括使用焊球安装到光子芯片的电IC。 这些焊接连接允许电子IC和光子芯片通信。 此外，发射机可以包括耦合到堆叠的PCB，使得PCB中的电信号被传输到IC和光子芯片（反之亦然）。 代替使用连接到光子芯片的表面上的焊盘的引线键将PCB耦合到堆叠，PCB的至少一部分设置在光子芯片和电气IC之间。 PCB还可以包括用于形成与电IC的直接焊接连接的接合焊盘。 因此，电IC可以包括与PCB和光子芯片两者的直接焊接连接。
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公开(公告)号：US20140248723A1
公开(公告)日：2014-09-04
申请号：US14276566
申请日：2014-05-13
Applicant: Cisco Technology, Inc.
Inventor： Kalpendu SHASTRI , Vipulkumar PATEL , Mark WEBSTER , Prakash GOTHOSKAR , Ravinder KACHRU , Soham PATHAK , Rao V. YELAMARTY , Thomas DAUGHERTY , Bipin DAMA , Kaushik PATEL , Kishor DESAI
CPC classification number: H01L25/50 , G02B6/423 , G02B6/4244 , G02B6/4245 , G02B6/4249 , G02B6/4257 , G02B6/426 , H01L25/167 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2924/00014
Abstract: A wafer scale implementation of an opto-electronic transceiver assembly process utilizes a silicon wafer as an optical reference plane and platform upon which all necessary optical and electronic components are simultaneously assembled for a plurality of separate transceiver modules. In particular, a silicon wafer is utilized as a “platform” (interposer) upon which all of the components for a multiple number of transceiver modules are mounted or integrated, with the top surface of the silicon interposer used as a reference plane for defining the optical signal path between separate optical components. Indeed, by using a single silicon wafer as the platform for a large number of separate transceiver modules, one is able to use a wafer scale assembly process, as well as optical alignment and testing of these modules.
Abstract translation: 光电子收发器组件过程的晶片级实现利用硅晶片作为光学参考平面和平台，同时为多个单独的收发器模块组装所有必需的光学和电子部件。 特别地，硅晶片被用作“平台”（插入器），在其上安装或集成多个收发器模块的所有组件，硅插入器的顶表面用作参考平面，用于定义 分离光学元件之间的光信号路径。 实际上，通过使用单个硅晶片作为大量单独的收发器模块的平台，可以使用晶片尺度组装过程以及这些模块的光学对准和测试。
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公开(公告)号：US20170244416A1
公开(公告)日：2017-08-24
申请号：US15048040
申请日：2016-02-19
Applicant: Cisco Technology, Inc.
Inventor： Kadaba LAKSHMIKUMAR , Mark Y. TSE , Bibhu DAS , Bipin DAMA
CPC classification number: H03L7/0807 , H03L7/087 , H03L7/093 , H03L7/095 , H03L7/113 , H04L7/0004 , H04L7/033 , H04L7/0331
Abstract: Embodiments herein describe a reference-less CDR circuit that receives electrical signals that may have been transmitted along either an electrical or optical interconnect which are then processed to identify the original data. To do so, the CDR circuit includes a frequency locking loop (FLL) and a phase locking loop (PLL) which generate control signals for a voltage controlled oscillator (VCO). In one embodiment, the FLL generates a coarse adjustment signal which the VCO uses to output a recovered clock that substantially matches the frequency of the received electrical signal. The PLL, on the other hand, generates a fine adjustment signal which the VCO uses to make small adjustments (e.g., half cycle phase shifts) to the recovered clock. The recovered clock outputted by the VCO is then fed back and used as an input in both the FLL and the PLL.
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公开(公告)号：US20150016784A1
公开(公告)日：2015-01-15
申请号：US14498669
申请日：2014-09-26
Applicant: Cisco Technology, Inc.
Inventor： Kalpendu SHASTRI , Soham PATHAK , Utpal CHAKRABARTI , Vipulkumar PATEL , Bipin DAMA , Ravinder KACHRU , Kishor DESAI
IPC: G02B6/42
CPC classification number: G02B6/4292 , B82Y20/00 , C03C15/00 , G02B6/136 , G02B6/4214 , G02B6/4246 , G02B6/4259 , Y10T29/4978
Abstract: An apparatus for providing self-aligned optical coupling between an opto-electronic substrate and a fiber array, where the substrate is enclosed by a transparent lid such that the associated optical signals enter and exit the arrangement through the transparent lid. The apparatus takes the form of a two-part connectorized fiber array assembly where the two pieces uniquely mate to form a self-aligned configuration. A first part, in the form of a plate, is attached to the transparent lid in the area where the optical signals pass through. The first plate includes a central opening with inwardly-tapering sidewalls surrounding its periphery. A second plate is also formed to include a central opening and has a lower protrusion with inwardly-tapering sidewalls that mate with the inwardly-tapering sidewalls of the first plate to form the self-aligned connectorized fiber array assembly. The fiber array is then attached to the second plate in a self-aligned fashion.
Abstract translation: 一种用于在光电子基板和光纤阵列之间提供自对准光耦合的装置，其中基板由透明盖包围，使得相关联的光信号通过透明盖进入和离开布置。 该装置采取两部分连接的光纤阵列组件的形式，其中两个部件独特地配合以形成自对准配置。 在光信号通过的区域中，透明盖附着有板的形式的第一部分。 第一板包括具有围绕其周边的向内逐渐变细的侧壁的中心开口。 第二板也形成为包括中心开口并且具有下突起，其具有向内渐缩的侧壁，与第一板的向内渐缩的侧壁配合形成自对准的连接纤维阵列组件。 然后将纤维阵列以自对准的方式附接到第二板。
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6.发明申请公开(公告)号：US20140294334A1
公开(公告)日：2014-10-02
申请号：US14218634
申请日：2014-03-18
Applicant: Cisco Technology, Inc.
Inventor： Kalpendu SHASTRI , Bipin DAMA , Mark WEBSTER , David PIEDE
CPC classification number: H01P3/00 , G02F1/011 , G02F1/0121 , G02F1/0327 , G02F1/225 , G02F1/2255 , G02F2201/124 , G02F2201/126 , H05K1/0245 , H05K2201/09245 , H05K2201/09254 , H05K2201/10121
Abstract: A configuration for routing electrical signals between a conventional electronic integrated circuit (IC) and an opto-electronic subassembly is formed as an array of signal paths carrying oppositely-signed signals on adjacent paths to lower the inductance associated with the connection between the IC and the opto-electronic subassembly. The array of signal paths can take the form of an array of wirebonds between the IC and the subassembly, an array of conductive traces formed on the opto-electronic subassembly, or both.
Abstract translation: 在常规电子集成电路（IC）和光电子组件之间布置电信号的配置被形成为在相邻路径上承载相反信号的信号路径阵列，以降低与IC和IC之间的连接相关联的电感 光电子组件。 信号路径阵列可以采取在IC和子组件之间的引线阵列的形式，形成在光电子组件上的导电迹线阵列，或两者。
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