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公开(公告)号：US09337121B2
公开(公告)日：2016-05-10
申请号：US14324724
申请日：2014-07-07
Inventor： Chi Hoon Jun , Sang Choon Ko , Seok-Hwan Moon , Woojin Chang , Sung-Bum Bae , Young Rak Park , Je Ho Na , Jae Kyoung Mun , Eun Soo Nam
IPC: H01L23/367 , H01L21/308 , H01L23/473 , H01L23/467 , H01L21/3065 , H01L21/3205
CPC classification number: H01L21/3065 , H01L21/3081 , H01L21/32051 , H01L23/367 , H01L23/467 , H01L23/473 , H01L2924/0002 , H01L2924/00
Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: an active region provided on a substrate; an inlet channel formed as a single cavity buried in one side of the substrate; an outlet channel formed as a single cavity buried in the other side of the substrate; a micro channel array comprising a plurality of micro channels, wherein the plurality of micro channels are formed as a plurality of cavities buried in the substrate, and one end of the micro channel array is connected to a side of the inlet channel and the other end of the micro channel array is connected to a side of the outlet channel; and a micro heat sink array separating the micro channels from one another.
Abstract translation: 提供半导体器件及其制造方法。 半导体器件包括：设置在衬底上的有源区; 入口通道形成为隐藏在所述基板的一侧中的单个腔; 出口通道形成为埋在基板的另一侧中的单个腔; 微通道阵列，其包括多个微通道，其中所述多个微通道形成为埋在所述衬底中的多个空腔，并且所述微通道阵列的一端连接到所述入口通道的一侧，而另一端 的微通道阵列连接到出口通道的一侧; 以及将微通道彼此分离的微型散热器阵列。
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公开(公告)号：US09224830B2
公开(公告)日：2015-12-29
申请号：US13914713
申请日：2013-06-11
Inventor： Seong-Il Kim , Jong-Won Lim , Dong Min Kang , Sang-Heung Lee , Hyung Sup Yoon , Chull Won Ju , Byoung-Gue Min , Jongmin Lee , Jae Kyoung Mun , Eun Soo Nam
IPC: H01L29/812 , H01L29/66 , H01L29/40 , H01L29/41 , H01L29/423 , H01L29/778 , H01L29/16 , H01L29/20
CPC classification number: H01L29/66477 , H01L29/1608 , H01L29/2003 , H01L29/40 , H01L29/401 , H01L29/402 , H01L29/41 , H01L29/42312 , H01L29/42316 , H01L29/42376 , H01L29/66462 , H01L29/7787 , H01L29/812
Abstract: A field effect transistor is provided. The transistor may include a source electrode and a drain electrode provided spaced apart from each other on a substrate and a ‘+’-shaped gate electrode provided on a portion of the substrate located between the source and drain electrodes.
Abstract translation: 提供场效应晶体管。 晶体管可以包括在基板上彼此间隔开设置的源电极和漏电极，以及设置在位于源极和漏极之间的基板的一部分上的“+”形栅电极。
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公开(公告)号：US08941231B2
公开(公告)日：2015-01-27
申请号：US13938324
申请日：2013-07-10
Inventor： Young Rak Park , Sang Choon Ko , Byoung-Gue Min , Jong-Won Lim , Hokyun Ahn , Sung-Bum Bae , Jae Kyoung Mun , Eun Soo Nam
IPC: H01L23/12 , H01L29/66 , H01L23/522 , H01L23/532 , H01L23/66
CPC classification number: H01L29/66477 , H01L23/5225 , H01L23/5228 , H01L23/5329 , H01L23/66 , H01L2223/6627 , H01L2223/6683 , H01L2924/0002 , H01L2924/00
Abstract: Provided are an electronic chip and a method of fabricating the same. The semiconductor chip may include a substrate, an active device integrated on the substrate, a lower interlayered insulating layer covering the resulting structure provided with the active device, a passive device provided on the lower interlayered insulating layer, an upper interlayered insulating layer covering the resulting structure provided with the passive device, and a ground electrode provided on the upper interlayered insulating layer. The upper interlayered insulating layer may be formed of a material, whose dielectric constant may be higher than that of the lower interlayered insulating layer.
Abstract translation: 提供一种电子芯片及其制造方法。 半导体芯片可以包括衬底，集成在衬底上的有源器件，覆盖所提供的有源器件的结构的下层间绝缘层，设置在下层间绝缘层上的无源器件，覆盖所得到的上层间绝缘层 设置有无源器件的结构，以及设置在上层间绝缘层上的接地电极。 上层间绝缘层可以由其介电常数可能高于下层间绝缘层的材料的材料形成。
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公开(公告)号：US08901608B2
公开(公告)日：2014-12-02
申请号：US13908076
申请日：2013-06-03
Inventor： Jong-Won Lim , Hokyun Ahn , Woojin Chang , Dong Min Kang , Seong-Il Kim , Sang-Heung Lee , Hyung Sup Yoon , Chull Won Ju , Hae Cheon Kim , Jae Kyoung Mun , Eun Soo Nam
IPC: H01L33/00 , H01L29/66 , H01L29/778
CPC classification number: H01L29/778 , H01L29/402 , H01L29/42316 , H01L29/66431
Abstract: A high electron mobility transistor includes a T-type gate electrode disposed on a substrate between source and drain electrodes and insulating layers disposed between the substrate and the T-type gate electrode. The insulating layers include first, second, and third insulating layers. The third insulating layer is disposed between the substrate and a head portion of the T-type gate electrode such that a portion of the third insulating layer is in contact with a foot portion of the T-type gate electrode. The second insulating layer is disposed between the substrate and the head portion of the T-type gate electrode to be in contact with the third insulating layer. The first insulating layer and another portion of the third insulating layer are sequentially stacked between the substrate and the head portion of the T-type gate electrode to be in contact with the second insulating layer.
Abstract translation: 高电子迁移率晶体管包括设置在源极和漏极之间的衬底上的T型栅电极和设置在衬底和T型栅电极之间的绝缘层。 绝缘层包括第一绝缘层，第二绝缘层和第三绝缘层。 第三绝缘层设置在基板和T型栅电极的头部之间，使得第三绝缘层的一部分与T型栅极的脚部接触。 第二绝缘层设置在基板与T型栅电极的头部之间以与第三绝缘层接触。 所述第一绝缘层和所述第三绝缘层的另一部分依次层叠在所述基板与所述T型栅电极的头部之间，以与所述第二绝缘层接触。
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公开(公告)号：US09825622B2
公开(公告)日：2017-11-21
申请号：US15217271
申请日：2016-07-22
Inventor： Woojin Chang , Sang Choon Ko , Jae Kyoung Mun , Young Rak Park
IPC: H03K17/687 , H03K17/081 , H03K17/74
CPC classification number: H03K17/08104 , H03K17/0822 , H03K17/74
Abstract: A cascode switch circuit includes a first transistor, a second transistor, and a protector. A first transistor receives a signal from a first terminal through a first end and transfers the signal to a second end in response to a first control signal. A second transistor delivers the signal that the first transistor transfers to a second terminal in response to a second control signal. A protector is connected between a gate of the first transistor and the second terminal. The first control signal is provided to allow the first transistor to operate in a normally-on state. The second control signal is provided to allow the second transistor to operate in a normally-off state.
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Patent Agency Ranking
公开(公告)号：US09362744B2
公开(公告)日：2016-06-07
申请号：US14040102
申请日：2013-09-27
Inventor： Yong il Jun , Sang Choon Ko , Jae Kyoung Mun , Dae Woo Lee , Kyu-Seok Lee , Ho Young Kim , Chul Won Ju
CPC classification number: H02J1/04 , H02H3/20 , H02H7/10 , H02M2001/0074 , H02M2001/0087 , Y10T307/406
Abstract: The inventive concept relates to a system supplying a constant current direct current power to serial loads connected in series with one another.The inventive concept is constituted by a constant current source power supply unit outputting a predetermined direct current, a load connection unit having the same rated current characteristic as the constant current source, a load connection unit having a rated current characteristic smaller than the constant current source, a load connection unit having a rated current characteristic greater than the constant current source, a load connection unit having a rated current characteristic greater or smaller than the constant current source and a circuit controlling or protecting them.
Abstract translation: 本发明的概念涉及向彼此串联连接的串联负载提供恒定电流直流电力的系统。 本发明的概念由输出预定直流电流的恒流源电源单元，与恒流源具有相同额定电流特性的负载连接单元构成，具有小于恒定电流源的额定电流特性的负载连接单元 具有大于恒流源的额定电流特性的负载连接单元，具有大于或小于恒流源的额定电流特性的负载连接单元和控制或保护恒流源的电路。
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公开(公告)号：US09209266B2
公开(公告)日：2015-12-08
申请号：US14555182
申请日：2014-11-26
Inventor： Jong-Won Lim , Ho Kyun Ahn , Young Rak Park , Dong Min Kang , Woo Jin Chang , Seong-il Kim , Sung Bum Bae , Sang-Heung Lee , Hyung Sup Yoon , Chull Won Ju , Jae Kyoung Mun , Eun Soo Nam
IPC: H01L21/265 , H01L21/336 , H01L21/28 , H01L29/66 , H01L29/423 , H01L29/778 , H01L29/16 , H01L21/311
CPC classification number: H01L29/66431 , H01L21/28255 , H01L21/31116 , H01L21/31144 , H01L29/1608 , H01L29/42316 , H01L29/42376 , H01L29/66068 , H01L29/7787
Abstract: Disclosed is a manufacturing method of a high electron mobility transistor. The method includes: forming a source electrode and a drain electrode on a substrate; forming a first insulating film having a first opening on an entire surface of the substrate, the first opening exposing a part of the substrate; forming a second insulating film having a second opening within the first opening, the second opening exposing a part of the substrate; forming a third insulating film having a third opening within the second opening, the third opening exposing a part of the substrate; etching a part of the first insulating film, the second insulating film and the third insulating film so as to expose the source electrode and the drain electrode; and forming a T-gate electrode on a support structure including the first insulating film, the second insulating film and the third insulating film.
Abstract translation: 公开了一种高电子迁移率晶体管的制造方法。 该方法包括：在基板上形成源电极和漏电极; 在所述基板的整个表面上形成具有第一开口的第一绝缘膜，所述第一开口暴露所述基板的一部分; 在所述第一开口内形成具有第二开口的第二绝缘膜，所述第二开口暴露所述基板的一部分; 在所述第二开口内形成具有第三开口的第三绝缘膜，所述第三开口暴露所述基板的一部分; 蚀刻第一绝缘膜，第二绝缘膜和第三绝缘膜的一部分，以使源电极和漏电极露出; 以及在包括第一绝缘膜，第二绝缘膜和第三绝缘膜的支撑结构上形成T栅电极。
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公开(公告)号：US09178474B2
公开(公告)日：2015-11-03
申请号：US13950895
申请日：2013-07-25
Inventor： Sang-Heung Lee , Seong-il Kim , Dong Min Kang , Jong-Won Lim , Chull Won Ju , Hyung Sup Yoon , Jae Kyoung Mun , Eun Soo Nam
CPC classification number: H03F3/08 , H03G1/0047 , H03G1/0088 , H03G3/02 , H03G3/3084 , H03G11/02
Abstract: Provided is a feedback amplifier. The feedback amplifier includes: an amplification circuit unit amplifying a burst packet signal inputted from an input terminal and outputting the amplified voltage to an output terminal; a feedback circuit unit disposed between the input terminal and the output terminal and controlling whether to apply a fixed resistance value to a signal outputted to the output terminal; a packet signal detection unit detecting a peak value of a burst packet signal from the output terminal and controlling whether to apply the fixed resistance value; and a bias circuit unit generating a bias voltage, wherein the feedback circuit unit determines a feedback resistance value to change the fixed resistance value in response to at least one control signal and adjusts a gain by receiving the bias voltage.
Abstract translation: 提供反馈放大器。 反馈放大器包括：放大电路单元，放大从输入端子输入的突发分组信号，并将放大的电压输出到输出端子; 反馈电路单元，设置在所述输入端子和所述输出端子之间，并且控制是否对输出到所述输出端子的信号施加固定电阻值; 分组信号检测单元，检测来自输出端的突发分组信号的峰值，并控制是否应用固定电阻值; 以及产生偏置电压的偏置电路单元，其中所述反馈电路单元确定反馈电阻值以响应于至少一个控制信号改变所述固定电阻值，并且通过接收所述偏置电压来调整增益。
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公开(公告)号：US09136396B2
公开(公告)日：2015-09-15
申请号：US13905213
申请日：2013-05-30
Inventor： Sang Choon Ko , Jae Kyoung Mun , Byoung-Gue Min , Young Rak Park , Hokyun Ahn , Jeong-Jin Kim , Eun Soo Nam
IPC: H01L29/66 , H01L29/808 , H01L29/417 , H01L29/778 , H01L29/43 , H01L29/45 , H01L29/20
CPC classification number: H01L29/808 , H01L21/76898 , H01L29/2003 , H01L29/4175 , H01L29/41758 , H01L29/432 , H01L29/454 , H01L29/66462 , H01L29/7786
Abstract: A method of manufacturing a semiconductor device includes forming devices including source, drain and gate electrodes on a front surface of a substrate including a bulk silicon, a buried oxide layer, an active silicon, a gallium nitride layer, and an aluminum-gallium nitride layer sequentially stacked, etching a back surface of the substrate to form a via-hole penetrating the substrate and exposing a bottom surface of the source electrode, conformally forming a ground interconnection on the back surface of the substrate having the via-hole, forming a protecting layer on the front surface of the substrate, and cutting the substrate to separate the devices from each other.
Abstract translation: 一种制造半导体器件的方法包括在包括体硅，掩埋氧化物层，活性硅，氮化镓层和铝 - 氮化镓层的衬底的前表面上形成包括源极，漏极和栅电极的器件 依次堆叠，蚀刻基板的背面以形成穿透基板的通孔并暴露源电极的底表面，在具有通孔的基板的背面上共形形成接地互连，形成保护 层，并且切割基板以将装置彼此分离。
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公开(公告)号：US08952422B2
公开(公告)日：2015-02-10
申请号：US13912350
申请日：2013-06-07
Inventor： Hokyun Ahn , Jong-Won Lim , Jeong-Jin Kim , Hae Cheon Kim , Jae Kyoung Mun , Eun Soo Nam
IPC: H01L29/66 , H01L29/423 , H01L29/778 , H01L29/20
CPC classification number: H01L29/7787 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/42316 , H01L29/4236 , H01L29/42376 , H01L29/51 , H01L29/518 , H01L29/66462 , H01L29/7786
Abstract: A field effect transistor includes an active layer and a capping layer sequentially stacked on a substrate, and a gate electrode penetrating the capping layer and being adjacent to the active layer. The gate electrode includes a foot portion adjacent to the active layer and a head portion having a width greater than a width of the foot portion. The foot portion of an end part of the gate electrode has a width less than a width of the head portion of another part of the gate electrode and greater than a width of the foot portion of the another part of the gate electrode. The foot portion of the end part of the gate electrode further penetrates the active layer so as to be adjacent to the substrate.
Abstract translation: 场效应晶体管包括依次层叠在基板上的有源层和覆盖层，以及贯穿封盖层并与活性层相邻的栅电极。 栅电极包括与有源层相邻的脚部和具有大于脚部的宽度的宽度的头部。 栅电极的端部的脚部的宽度小于栅电极的另一部分的头部的宽度，并且大于栅极的另一部分的脚部的宽度。 栅电极的端部的脚部进一步穿过有源层，以与衬底相邻。
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