公开(公告)号：US20200013678A1

公开(公告)日：2020-01-09

申请号：US16026130

申请日：2018-07-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sipeng Gu ,  Akshey Sehgal ,  Xinyuan Dou ,  Sunil K. Singh ,  Ravi P. Srivastava ,  Haiting Wang ,  Scott H. Beasor

IPC: H01L21/8234 ,  H01L29/08 ,  H01L29/423 ,  H01L23/48 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/49 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/66

Abstract: This disclosure is directed to an integrated circuit (IC) structure. The IC structure may include a semiconductor structure including two source/drain regions; a metal gate positioned on the semiconductor structure adjacent to and between the source/drain regions; a metal cap with a different metal composition than the metal gate and having a thickness in the range of approximately 0.5 nanometer (nm) to approximately 5 nm positioned on the metal gate; a first dielectric cap layer positioned above the semiconductor structure; an inter-layer dielectric (ILD) positioned above the semiconductor structure and laterally abutting both the metal cap and the metal gate, wherein an upper surface of the ILD has a greater height above the semiconductor structure than an upper surface of the metal gate; a second dielectric cap layer positioned on the ILD and above the metal cap; and a contact on and in electrical contact with the metal cap.

公开(公告)号：US09576894B2

公开(公告)日：2017-02-21

申请号：US14729188

申请日：2015-06-03

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Sunil Kumar Singh ,  Ravi Prakash Srivastava ,  Xusheng Wu ,  Akshey Sehgal ,  Teck Jung Tang

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L21/311

CPC classification number: H01L23/5226 ,  H01L21/02118 ,  H01L21/02167 ,  H01L21/02282 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76811 ,  H01L23/53238 ,  H01L23/53295

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes depositing an organic dielectric material overlying a semiconductor substrate for forming an organic interlayer dielectric (OILD) layer. An opening is formed in the OILD layer and a conductive metal fill is deposited in the opening for forming a metal line and/or a via.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个示例中，制造集成电路的方法包括沉积覆盖在用于形成有机层间电介质（OILD）层的半导体衬底上的有机电介质材料。 在OILD层中形成开口，并且在用于形成金属线和/或通孔的开口中沉积导电金属填充物。

公开(公告)号：US20150348913A1

公开(公告)日：2015-12-03

申请号：US14818039

申请日：2015-08-04

Applicant: Globalfoundries Inc.

Inventor： Xiang Hu ,  Lokesh Subramany ,  Alok Vaid ,  Sipeng Gu ,  Akshey Sehgal

IPC: H01L23/544 ,  H01L29/06 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L23/544 ,  H01L21/3083 ,  H01L21/3086 ,  H01L22/30 ,  H01L27/0886 ,  H01L29/0692 ,  H01L29/16 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Approaches for providing a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. A previously deposited amorphous carbon layer can be removed from over a mandrel that has been previously formed on a subset of a substrate, such as using a photoresist. A pad hardmask can be formed over the mandrel on the subset of the substrate. This formation results in the subset of the substrate having the pad hardmask covering the mandrel thereon and the remainder of the substrate having the amorphous carbon layer covering the mandrel thereon. This amorphous carbon layer can be removed from over the mandrel on the remainder of the substrate, allowing a set of fins to be formed therein while the amorphous carbon layer keeps the set of fins from being formed in the portion of the substrate that it covers.

Abstract translation: 公开了一种用于提供与翅片场效应晶体管（FinFET）器件的一组翅片相邻的平面计量垫的方法。 先前沉积的非晶碳层可以从预先形成在基底的子集上的心轴上去除，例如使用光致抗蚀剂。 衬垫硬掩模可以在衬底的子集上的心轴上形成。 这种形成导致衬底的子集具有覆盖其上的心轴的衬垫硬掩模，并且具有覆盖其上的心轴的无定形碳层的衬底的其余部分。 该无定形碳层可以在基体的其余部分上从心轴上除去，允许在其中形成一组翅片，而无定形碳层保持该组翅片不会形成在其所覆盖的基底部分中。

公开(公告)号：US20150270175A1

公开(公告)日：2015-09-24

申请号：US14219059

申请日：2014-03-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiang Hu ,  Andy Chih-Hung Wei ,  Dae-han Choi ,  Mariappan Hariharaputhiran ,  Weihua Tong ,  Dae Geun Yang ,  Akshey Sehgal ,  Jing Wan

IPC: H01L21/8234 ,  H01L21/027 ,  H01L21/306 ,  H01L21/324 ,  H01L29/78 ,  H01L21/308

CPC classification number: H01L21/823431 ,  H01L21/268 ,  H01L21/3081 ,  H01L21/3086 ,  H01L29/66795

Abstract: Provided herein are approaches for forming a fin field-effect-transistor (FinFET) device using a partially crystallized fin hard mask. Specifically, a hard mask is patterned over a substrate, and the FinFET device is annealed to form a set of crystallized hard mask elements adjacent a set of non-crystallized hard mask elements. A masking structure is provided over a first section of the patterned hard mask to prevent the set of non-crystallized hard mask elements from being crystallized during the anneal. During a subsequent fin cut process, the non-crystallized mask elements are removed, while crystallized mask elements remain. A set of fins is then formed in the FinFET device according to the location(s) of the crystallized mask elements.

Abstract translation: 本文提供了使用部分结晶的翅片硬掩模形成鳍状场效应晶体管（FinFET）器件的方法。 具体地说，将硬掩模图案化在衬底上，并且FinFET器件被退火以形成与一组非结晶硬掩模元件相邻的一组结晶的硬掩模元件。 在图案化的硬掩模的第一部分上提供掩模结构，以防止在退火期间该组非结晶硬掩模元件结晶。 在随后的翅片切割过程中，除去未结晶的掩模元件，同时保留结晶的掩模元件。 然后根据结晶化掩模元件的位置在FinFET器件中形成一组翅片。

公开(公告)号：US10134876B2

公开(公告)日：2018-11-20

申请号：US15475873

申请日：2017-03-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bharat V. Krishnan ,  Timothy J. McArdle ,  Rinus Tek Po Lee ,  Shishir K. Ray ,  Akshey Sehgal

IPC: H01L27/088 ,  H01L21/336 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to finFETs with strained channels and reduced on state resistances and methods of manufacture. The structure includes: a plurality of fin structures comprising doped source and drain regions with a diffusion blocking layer between the doped source and drain regions and an underlying fin region formed within dielectric material.

公开(公告)号：US20170025347A1

公开(公告)日：2017-01-26

申请号：US15043011

申请日：2016-02-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sunil K. Singh ,  Ravi P. Srivastava ,  Mark A. Zaleski ,  Akshey Sehgal

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/31051 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76892 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide a semiconductor structure for BEOL (back end of line) integration. A directed self assembly (DSA) material is deposited and annealed to form two distinct phase regions. One of the phase regions is selectively removed, and the remaining phase region serves as a mask for forming cavities in an underlying layer of metal and/or dielectric. The process is then repeated to form complex structures with patterns of metal separated by dielectric regions.

Abstract translation: 本发明的实施例提供了一种用于BEOL（后端）集成的半导体结构。 定向自组装（DSA）材料被沉积并退火以形成两个不同的相位区域。 选择性地去除一个相区，并且剩余的相区用作在金属和/或电介质的下层中形成空腔的掩模。 然后重复该过程以形成具有由电介质区域分离的金属图案的复杂结构。

公开(公告)号：US09105507B2

公开(公告)日：2015-08-11

申请号：US14595924

申请日：2015-01-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy C. Wei ,  Akshey Sehgal ,  Seung Y. Kim ,  Teck Jung Tang ,  Francis M. Tambwe

IPC: H01L29/76 ,  H01L29/10 ,  H01L27/088

CPC classification number: H01L29/1083 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  Y10S257/903

Abstract: A FinFET device includes a plurality of fin structures positioned in and above a semiconducting substrate, wherein each of the fin structures includes a first portion of the semiconducting substrate, an undoped layer of semiconducting material positioned above the first portion of the semiconducting substrate, and a dopant-containing layer of semiconducting material positioned between the first portion of the semiconducting substrate and the undoped semiconducting material, wherein the dopant material is adapted to retard diffusion of one of boron and phosphorous. A gate electrode is positioned around at least the undoped layer of semiconducting material of each of the plurality of fin structures, wherein a height level of a bottom surface of the gate electrode is positioned approximately level with or lower than a height level of a bottom of the undoped layer of semiconducting material of each of the plurality of fin structures.

Abstract translation: FinFET器件包括位于半导体衬底中和上方的多个翅片结构，其中每个翅片结构包括半导体衬底的第一部分，位于半导体衬底的第一部分上方的未掺杂的半导体材料层，以及 位于半导体衬底的第一部分和未掺杂的半导体材料之间的半导体材料含掺杂剂层，其中掺杂剂材料适于延迟硼和磷中的一种的扩散。 栅电极至少围绕多个翅片结构中的每一个的半导体材料的未掺杂层定位，其中栅电极的底表面的高度水平位于与底部的高度水平近似等于或低于 所述多个翅片结构中的每一个的未掺杂的半导体材料层。

公开(公告)号：US10714380B2

公开(公告)日：2020-07-14

申请号：US16171477

申请日：2018-10-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ravi P. Srivastava ,  Sipeng Gu ,  Sunil K. Singh ,  Xinyuan Dou ,  Akshey Sehgal ,  Zhiguo Sun

IPC: H01L21/768 ,  H01L21/02

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to smooth sidewall structures and methods of manufacture. The method includes: forming a plurality of mandrel structures; forming a first spacer material on each of the plurality of mandrel structures; forming a second spacer material over the first spacer material; and removing the first spacer material and the plurality of mandrel structures to form a sidewall structure having a sidewall smoothness greater than the plurality of mandrel structures.

公开(公告)号：US09105478B2

公开(公告)日：2015-08-11

申请号：US14064840

申请日：2013-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Wei ,  Mariappan Hariharaputhiran ,  Dae Geun Yang ,  Dae-Han Choi ,  Xiang Hu ,  Richard J. Carter ,  Akshey Sehgal

IPC: H01L21/302 ,  H01L21/033 ,  G03F1/50

CPC classification number: H01L21/0332 ,  G03F1/50 ,  H01L21/0276 ,  H01L21/0334 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/823821 ,  H01L29/785

Abstract: Devices and methods for forming semiconductor devices with fins at tight fin pitches are provided. One method includes, for instance: obtaining an intermediate semiconductor device; growing an epi layer over the substrate; forming a doped layer below the epi layer; depositing a first oxide layer on the epi layer; applying a dielectric material on the first oxide layer; and depositing a lithography stack on the dielectric material. One intermediate semiconductor device includes, for instance: a substrate with at least one n-well region and at least one p-well region; a doped layer over the substrate; an epi layer over the doped layer; a first oxide layer over the epi layer; a dielectric layer over the first oxide layer; and a lithography stack over the dielectric layer.

Abstract translation: 提供了用于以紧密翅片间距形成翅片的半导体器件的装置和方法。 一种方法包括，例如：获得中间半导体器件; 在衬底上生长表层; 在外延层下方形成掺杂层; 在外延层上沉积第一氧化物层; 在第一氧化物层上施加电介质材料; 以及在介电材料上沉积光刻叠层。 一个中间半导体器件包括例如：具有至少一个n阱区和至少一个p阱区的衬底; 衬底上的掺杂层; 掺杂层上的外延层; 在epi层上的第一氧化物层; 第一氧化物层上的介电层; 以及介电层上的光刻叠层。

公开(公告)号：US20150123214A1

公开(公告)日：2015-05-07

申请号：US14595924

申请日：2015-01-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy C. Wei ,  Akshey Sehgal ,  Seung Y. Kim ,  Teck Jung Tang ,  Francis M. Tambwe

IPC: H01L29/10 ,  H01L27/088

CPC classification number: H01L29/1083 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  Y10S257/903

Abstract: A FinFET device includes a plurality of fin structures positioned in and above a semiconducting substrate, wherein each of the fin structures includes a first portion of the semiconducting substrate, an undoped layer of semiconducting material positioned above the first portion of the semiconducting substrate, and a dopant-containing layer of semiconducting material positioned between the first portion of the semiconducting substrate and the undoped semiconducting material, wherein the dopant material is adapted to retard diffusion of one of boron and phosphorous. A gate electrode is positioned around at least the undoped layer of semiconducting material of each of the plurality of fin structures, wherein a height level of a bottom surface of the gate electrode is positioned approximately level with or lower than a height level of a bottom of the undoped layer of semiconducting material of each of the plurality of fin structures.

Abstract translation: FinFET器件包括位于半导体衬底中和上方的多个翅片结构，其中每个翅片结构包括半导体衬底的第一部分，位于半导体衬底的第一部分上方的未掺杂的半导体材料层，以及 位于半导体衬底的第一部分和未掺杂的半导体材料之间的半导体材料含掺杂剂层，其中掺杂剂材料适于延迟硼和磷中的一种的扩散。 栅电极至少围绕多个翅片结构中的每一个的半导体材料的未掺杂层定位，其中栅电极的底表面的高度水平位于与底部的高度水平近似等于或低于 所述多个翅片结构中的每一个的未掺杂的半导体材料层。