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    DETECTING A VOID BETWEEN A VIA AND A WIRING LINE
    4.
    发明申请
    DETECTING A VOID BETWEEN A VIA AND A WIRING LINE 审中-公开
    检测威盛和线路之间的空位

    公开(公告)号：US20160370421A1

    公开(公告)日：2016-12-22

    申请号：US14743208

    申请日：2015-06-18

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Griselda Bonilla ,  Samuel S. S. Choi ,  Ronald G. Filippi ,  Elbert E. Huang ,  Naftali E. Lustig ,  Andrew H. Simon

    IPC: G01R31/26 ,  G01R31/02 ,  H01L21/66 ,  H01L23/528 ,  H01L23/522

    CPC classification number: H01L22/12 ,  G01R31/2853 ,  H01L22/14 ,  H01L22/34

    Abstract: A semiconductor device includes a first circuit structure and a second circuit structure. The first circuit structure includes a wiring line and a via upon and electrically contacting the wiring line. The via induces lateral etching voids between the via and the wiring line below the via upon the surface of the wiring line. The second circuit structure includes a similar wiring line, relative to the reference wiring line, without or fewer via thereupon. The first circuit structure is therefore relatively more prone to lateral etching void formation as compared to the second circuit structure. Resistances are measured across the first circuit structure and the second circuit structure and compared against a comparison threshold to determine whether the first circuit structure includes one or more lateral etching voids. If the first structure is deemed to not include lateral etching voids, the fabrication process of the device may be deemed reliable.

    Abstract translation: 半导体器件包括第一电路结构和第二电路结构。 第一电路结构包括在布线和电接触布线之间的布线和通孔。 该通孔在布线的表面上的通孔下方的通孔和布线之间引起横向蚀刻空隙。 第二电路结构包括相对于参考布线的类似的布线，没有或更少的通孔。 因此，与第二电路结构相比，第一电路结构相对更倾向于侧向蚀刻空隙形成。 在第一电路结构和第二电路结构上测量电阻，并与比较阈值进行比较，以确定第一电路结构是否包括一个或多个横向蚀刻空隙。 如果第一结构被认为不包括侧向蚀刻空隙，则该装置的制造过程可以被认为是可靠的。

    FORMING AIR GAP
    8.
    发明申请
    FORMING AIR GAP 审中-公开

    公开(公告)号：US20180076082A1

    公开(公告)日：2018-03-15

    申请号：US15813399

    申请日：2017-11-15

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Samuel S. Choi ,  Ronald G. Filippi ,  Elbert E. Huang ,  Naftali E. Lustig ,  Griselda Bonilla ,  Andrew H. Simon

    IPC: H01L21/768 ,  H01L23/532 ,  H01L21/02 ,  H01L21/311 ,  H01L23/528

    CPC classification number: H01L21/7682 ,  H01L21/0217 ,  H01L21/31111 ,  H01L21/31144 ,  H01L23/528 ,  H01L23/5329

    Abstract: A method of forming an air gap for a semiconductor device and the device formed are disclosed. The method may include forming an air gap mask layer over a dielectric interconnect layer, the dielectric interconnect layer including a dielectric layer having a conductive interconnect therein and a cap layer over the dielectric layer; patterning the air gap mask layer using extreme ultraviolet (EUV) light and etching to form an air gap mask including an opening in the cap layer exposing a portion of the dielectric layer of the dielectric interconnect layer adjacent to the conductive interconnect; removing the air gap mask; etching an air gap space adjacent to the conductive interconnect within the dielectric layer of the dielectric interconnect layer using the opening in the cap layer; and forming an air gap in the dielectric interconnect layer by depositing an air gap capping layer to seal the air gap space.

    Forming air gap
    10.
    发明授权
    Forming air gap 有权

    公开(公告)号：US10224236B2

    公开(公告)日：2019-03-05

    申请号：US15813399

    申请日：2017-11-15

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Samuel S. Choi ,  Ronald G. Filippi ,  Elbert E. Huang ,  Naftali E. Lustig ,  Griselda Bonilla ,  Andrew H. Simon

    IPC: H01L21/768 ,  H01L21/311 ,  H01L23/528 ,  H01L21/02 ,  H01L23/532

    Abstract: A method of forming an air gap for a semiconductor device and the device formed are disclosed. The method may include forming an air gap mask layer over a dielectric interconnect layer, the dielectric interconnect layer including a dielectric layer having a conductive interconnect therein and a cap layer over the dielectric layer; patterning the air gap mask layer using extreme ultraviolet (EUV) light and etching to form an air gap mask including an opening in the cap layer exposing a portion of the dielectric layer of the dielectric interconnect layer adjacent to the conductive interconnect; removing the air gap mask; etching an air gap space adjacent to the conductive interconnect within the dielectric layer of the dielectric interconnect layer using the opening in the cap layer; and forming an air gap in the dielectric interconnect layer by depositing an air gap capping layer to seal the air gap space.

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