公开(公告)号：US09574287B2

公开(公告)日：2017-02-21

申请号：US14038139

申请日：2013-09-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Can Bayram ,  Christos D. Dimitrakopoulos ,  Keith E. Fogel ,  Jeehwan Kim ,  John A. Ott ,  Devendra K. Sadana

IPC: C30B25/00 ,  C30B25/18 ,  C30B29/40 ,  H01L21/02 ,  H01L29/16 ,  H01L33/00 ,  H01L33/32 ,  C30B29/02 ,  H01L33/12

CPC classification number: C30B25/18 ,  C30B25/183 ,  C30B29/02 ,  C30B29/406 ,  H01L21/0254 ,  H01L29/1606 ,  H01L33/0025 ,  H01L33/0079 ,  H01L33/12 ,  H01L33/32

Abstract: A method of forming an epitaxial semiconductor material that includes forming a graphene layer on a semiconductor and carbon containing substrate and depositing a metal containing monolayer on the graphene layer. An epitaxial layer of a gallium containing material is formed on the metal containing monolayer. A layered stack of the metal containing monolayer and the epitaxial layer of gallium containing material is cleaved from the graphene layer that is present on the semiconductor and carbon containing substrate.

Abstract translation: 一种形成外延半导体材料的方法，其包括在半导体和含碳衬底上形成石墨烯层并在所述石墨烯层上沉积含金属的单层。 在含金属单层上形成含镓材料的外延层。 含有金属的单层的层叠堆叠和含镓材料的外延层从存在于半导体和含碳衬底上的石墨烯层切割。

公开(公告)号：US20160343623A1

公开(公告)日：2016-11-24

申请号：US14718760

申请日：2015-05-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Dominic J. Schepis

IPC: H01L21/8238 ,  H01L29/10 ,  H01L27/092

CPC classification number: H01L21/823878 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823892 ,  H01L27/0924 ,  H01L29/1083 ,  H01L29/66803 ,  H01L29/785

Abstract: A punch through stop layer is formed in a bulk FinFET structure using doped oxides. Dopants are driven into the substrate and base portions of the fins by annealing. The punch through stop layer includes a p-type region and an n-type region, both of which may extend substantially equal distances into the semiconductor fins.

Abstract translation: 通过使用掺杂氧化物的体积FinFET结构形成穿通停止层。 通过退火将掺杂剂驱入散热片的基板和基部。 穿通停止层包括p型区域和n型区域，它们都可以延伸到半导体鳍片中基本相等的距离。

公开(公告)号：US20160190302A1

公开(公告)日：2016-06-30

申请号：US14585742

申请日：2014-12-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Dominic J. Schepis

IPC: H01L29/78 ,  H01L29/161 ,  H01L29/06 ,  H01L29/167 ,  H01L21/84 ,  H01L21/02 ,  H01L21/322 ,  H01L21/324 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/785 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/7624 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device where: (i) the fins are formed over a porous semiconductor material layer (for example, a silicon layer); and (ii) the porous semiconductor layer is then oxidized to form an insulator layer (for example, a SiO2 buried oxide layer). The pores in the porous semiconductor layer facilitate reliable oxidation of the insulator layer by allowing penetration of gaseous oxygen (O2) throughout the layer as it is oxidized to form the insulator layer. In some of these embodiments, a thin non-porous semiconductor layer is located over the porous semiconductor layer (prior to its oxidation) to allow strained epitaxial growth of material to be used in making source regions and drain regions of the finished semiconductor device (for example, a FINFET).

Abstract translation: 一种制造半导体器件的方法，其中：（i）所述散热片形成在多孔半导体材料层（例如，硅层）上; 和（ii）然后氧化多孔半导体层以形成绝缘体层（例如，SiO 2掩埋氧化物层）。 多孔半导体层中的孔促进了绝缘体层的可靠氧化，允许气态氧（O 2）在整个层中被氧化以形成绝缘体层。 在这些实施例的一些中，薄的无孔半导体层位于多孔半导体层之上（在其氧化之前），以允许材料的应变外延生长用于制造成品半导体器件的源极区域和漏极区域（用于 例如，FINFET）。

公开(公告)号：US09236271B2

公开(公告)日：2016-01-12

申请号：US13749330

申请日：2013-01-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Can Bayram ,  Stephen W. Bedell ,  Devendra K. Sadana ,  Katherine L. Saenger

IPC: H01L21/30 ,  H01L21/46 ,  H01L21/428 ,  H01L21/18 ,  H01L33/00 ,  H01L21/683

CPC classification number: H01L21/428 ,  H01L21/18 ,  H01L21/185 ,  H01L21/6835 ,  H01L21/6836 ,  H01L33/0079 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2221/68386

Abstract: A pulsed laser-initiated exfoliation method for patterning a Group III-nitride film on a growth substrate is provided. This method includes providing a Group III-nitride film a growth substrate, wherein a growth substrate/Group III-nitride film interface is present between the Group III-nitride film and the growth substrate. Next, a laser is selected that provides radiation at a wavelength at which the Group III-nitride film is transparent and the growth substrate is absorbing. The interface is then irradiated with pulsed laser radiation from the Group III-nitride film side of the growth substrate/Group III-nitride film interface to exfoliate a region of the Group III-nitride from the growth substrate. A method for transfer a Group-III nitride film from a growth substrate to a handle substrate is also provided.

Abstract translation: 提供了用于在生长衬底上图案化III族氮化物膜的脉冲激光起始剥离方法。 该方法包括提供III族氮化物膜生长衬底，其中在III族氮化物膜和生长衬底之间存在生长衬底/ III族氮化物膜界面。 接下来，选择提供在III族氮化物膜透明并且生长衬底吸收的波长处的辐射的激光。 然后用生长衬底/ III族氮化物膜界面的III族氮化物膜侧的脉冲激光辐射照射该界面，以从生长衬底剥离III族氮化物的区域。 还提供了将III族氮化物膜从生长衬底转移到手柄衬底的方法。

公开(公告)号：US09218962B2

公开(公告)日：2015-12-22

申请号：US14057064

申请日：2013-10-18

Applicant: GLOBALFOUNDRIES INC. ,  Matheson Tri-Gas, Inc.

Inventor： Paul D. Brabant ,  Keith Chung ,  Hong He ,  Devendra K. Sadana ,  Manabu Shinriki

IPC: H01L21/36 ,  H01L21/20 ,  H01L21/02 ,  C30B25/02 ,  C30B29/52

CPC classification number: H01L21/02532 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/02636

Abstract: A high order silane having a formula of SinH2n+2, in which n is an integer greater than 3, in combination with a germanium precursor gas is employed to deposit an epitaxial semiconductor alloy material including at least silicon and germanium on a single crystalline surface. The germanium precursor gas effectively reduces the gas phase reaction of the high order silane, thereby improving the thickness uniformity of the deposited epitaxial semiconductor alloy material. The combination of the high order silane and the germanium precursor gas provides a high deposition rate in the Frank-van der Merwe growth mode for deposition of a single crystalline semiconductor alloy material.

Abstract translation: 使用与锗前体气体组合的具有式SinH2n + 2的其中n为大于3的整数的高级硅烷在单一结晶表面上沉积至少包含硅和锗的外延半导体合金材料。 锗前体气体有效地降低了高级硅烷的气相反应，从而提高了沉积的外延半导体合金材料的厚度均匀性。 高阶硅烷和锗前体气体的组合在用于沉积单晶半导体合金材料的Frank-van der Merwe生长模式中提供高沉积速率。

公开(公告)号：US09391180B2

公开(公告)日：2016-07-12

申请号：US14725755

申请日：2015-05-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bahman Hekmatshoar-Tabari ,  Tak H. Ning ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L29/66 ,  H01L29/737 ,  H01L21/02 ,  H01L29/735 ,  H01L29/16 ,  H01L29/165 ,  H01L21/265 ,  H01L21/30 ,  H01L29/08 ,  H01L29/10 ,  H01L29/36 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/737 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/265 ,  H01L21/3003 ,  H01L29/0817 ,  H01L29/1004 ,  H01L29/1604 ,  H01L29/165 ,  H01L29/36 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/66242 ,  H01L29/735

Abstract: Heterojunction bipolar transistors are provided that include at least one contact (e.g., collector, emitter, and/or base) formed by a heterojunction between a crystalline semiconductor material and a doped non-crystalline semiconductor material layer. An interfacial intrinsic non-crystalline semiconductor material layer is present at the heterojunction between the crystalline semiconductor material and the doped non-crystalline semiconductor material layer. The presence of the interfacial intrinsic non-crystalline semiconductor material layer improves the surface passivation of the crystalline semiconductor material by reducing the interface defect density at the heterojunction.

公开(公告)号：US09391144B2

公开(公告)日：2016-07-12

申请号：US14725581

申请日：2015-05-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Can Bayram ,  Cheng-Wei Cheng ,  Devendra K. Sadana ,  Kuen-Ting Shiu

IPC: H01L29/20 ,  H01L21/02 ,  H01L29/04 ,  H01L23/528 ,  H01L27/088 ,  H01L29/205 ,  H01L33/00 ,  H01L33/12

CPC classification number: H01L29/2003 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/02658 ,  H01L23/528 ,  H01L27/088 ,  H01L29/04 ,  H01L29/045 ,  H01L29/205 ,  H01L33/007 ,  H01L33/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure including a (100) silicon substrate having a plurality openings located within the silicon substrate, wherein each opening exposes a surface of the silicon substrate having a (111) crystal plane. This structure further includes an epitaxial semiconductor material located on an uppermost surface of the (100) silicon substrate, and a gallium nitride material located adjacent to the surface of the silicon substrate having the (111) crystal plane and adjacent a portion of the epitaxial semiconductor material. The structure also includes at least one semiconductor device located upon and within the gallium nitride material and at least one other semiconductor device located upon and within the epitaxial semiconductor material.

Abstract translation: 一种半导体结构，包括具有位于硅衬底内的多个开口的（100）硅衬底，其中每个开口暴露具有（111）晶面的硅衬底的表面。 该结构还包括位于（100）硅衬底的最上表面上的外延半导体材料和位于与具有（111）晶面并且与外延半导体的一部分相邻的硅衬底的表面附近的氮化镓材料 材料。 该结构还包括位于氮化镓材料之上和之内的至少一个半导体器件和位于外延半导体材料之上和之内的至少一个其它半导体器件。

公开(公告)号：US09601624B2

公开(公告)日：2017-03-21

申请号：US14585742

申请日：2014-12-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Dominic J. Schepis

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/161 ,  H01L29/06 ,  H01L21/84 ,  H01L21/02 ,  H01L29/167 ,  H01L21/762

CPC classification number: H01L29/785 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/7624 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device where: (i) the fins are formed over a porous semiconductor material layer (for example, a silicon layer); and (ii) the porous semiconductor layer is then oxidized to form an insulator layer (for example, a SiO2 buried oxide layer). The pores in the porous semiconductor layer facilitate reliable oxidation of the insulator layer by allowing penetration of gaseous oxygen (O2) throughout the layer as it is oxidized to form the insulator layer. In some of these embodiments, a thin non-porous semiconductor layer is located over the porous semiconductor layer (prior to its oxidation) to allow strained epitaxial growth of material to be used in making source regions and drain regions of the finished semiconductor device (for example, a FINFET).

公开(公告)号：US09514995B1

公开(公告)日：2016-12-06

申请号：US14718760

申请日：2015-05-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Dominic J. Schepis

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10

CPC classification number: H01L21/823878 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823892 ,  H01L27/0924 ,  H01L29/1083 ,  H01L29/66803 ,  H01L29/785

Abstract: A punch through stop layer is formed in a bulk FinFET structure using doped oxides. Dopants are driven into the substrate and base portions of the fins by annealing. The punch through stop layer includes a p-type region and an n-type region, both of which may extend substantially equal distances into the semiconductor fins.

Abstract translation: 通过使用掺杂氧化物的体积FinFET结构形成穿通停止层。 通过退火将掺杂剂驱入散热片的基板和基部。 穿通停止层包括p型区域和n型区域，它们都可以延伸到半导体鳍片中基本相等的距离。

公开(公告)号：US09508640B2

公开(公告)日：2016-11-29

申请号：US13940874

申请日：2013-07-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Cheng-Wei Cheng ,  Szu-Lin Cheng ,  Keith E. Fogel ,  Edward W. Kiewra ,  Amlan Majumdar ,  Devendra K. Sadana ,  Kuen-Ting Shiu ,  Yanning Sun

IPC: H01L21/00 ,  H01L23/522 ,  H01L23/485 ,  H01L21/8238 ,  H01L27/12

CPC classification number: H01L23/5226 ,  H01L21/823807 ,  H01L21/823878 ,  H01L23/485 ,  H01L27/1207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a device with a multi-tiered contact structure includes forming first contacts in via holes down to a first level, forming a dielectric capping layer over exposed portions of the first contacts and forming a dielectric layer over the capping layer. Via holes are opened in the dielectric layer down to the capping layer. Holes are opened in the capping layer through the via holes to expose the first contacts. Contact connectors and second contacts are formed in the via holes such that the first and second contacts are connected through the capping layer by the contact connectors to form multi-tiered contacts.

Abstract translation: 用于形成具有多层接触结构的器件的方法包括将通孔中的第一触点形成为第一级，在第一触点的暴露部分上形成电介质覆盖层，并在覆盖层上形成电介质层。 通孔在电介质层中向下开到封盖层。 孔通过通孔在封盖层中打开以露出第一触点。 接触连接器和第二触点形成在通孔中，使得第一和第二触点通过接触连接器通过覆盖层连接以形成多层接触。