公开(公告)号：US20150253667A1

公开(公告)日：2015-09-10

申请号：US14642328

申请日：2015-03-09

Applicant: Intel Corporation

Inventor： ROBERT L. BRISTOL ,  PAUL A. NYHUS ,  CHARLES H. WALLACE

IPC: G03F7/095 ,  H01L21/033 ,  H01L21/027

CPC classification number: G03F7/095 ,  G03F7/0002 ,  G03F7/0035 ,  G03F7/0043 ,  G03F7/0045 ,  G03F7/094 ,  G03F7/2037 ,  G03F7/2039 ,  G03F7/2041 ,  G03F7/38 ,  H01L21/0274 ,  H01L21/0334 ,  Y10S430/143 ,  Y10S430/168 ,  Y10T428/24851

Abstract: A method of fabricating a substrate including coating a first resist onto a hardmask, exposing regions of the first resist to electromagnetic radiation at a dose of 10.0 mJ/cm2 or greater and removing a portion of said the and forming guiding features. The method also includes etching the hardmask to form isolating features in the hardmask, applying a second resist within the isolating features forming regions of the second resist in the hardmask, and exposing regions of the second resist to electromagnetic radiation having a dose of less than 10.0 mJ/cm2 and forming elements.

Abstract translation: 一种制造衬底的方法，包括将第一抗蚀剂涂覆在硬掩模上，将第一抗蚀剂的区域以10.0mJ / cm 2或更大的剂量暴露于电磁辐射，并去除所述和形成引导特征的一部分。 该方法还包括蚀刻硬掩模以在硬掩模中形成隔离特征，在形成硬掩模中的第二抗蚀剂的区域的隔离特征内施加第二抗蚀剂，以及将第二抗蚀剂的区域暴露于具有小于10.0的剂量的电磁辐射 mJ / cm 2和成形元件。

公开(公告)号：US20170207185A1

公开(公告)日：2017-07-20

申请号：US15475793

申请日：2017-03-31

Applicant: INTEL CORPORATION

Inventor： CHARLES H. WALLACE ,  HOSSAM A. ABDALLAH ,  ELLIOT N. TAN ,  SWAMINATHAN SIVAKUMAR ,  OLEG GOLONZKA ,  ROBERT M. BIGWOOD

IPC: H01L23/00 ,  H01L21/306 ,  G03F7/16 ,  H01L21/308 ,  G03F7/00 ,  G03F7/40

Abstract: Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may be arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern. The pattern decomposition techniques may be integrated into any number of patterning processes, such as litho-freeze-litho-etch and litho-etch-litho-etch patterning processes.

公开(公告)号：US20160197011A1

公开(公告)日：2016-07-07

申请号：US14912036

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： ROBERT L. BRISTOL ,  FLORIAN GSTREIN ,  RICHARD E. SCHENKER ,  PAUL A. NYHUS ,  CHARLES H. WALLACE ,  HUI JAE YOO

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76825 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Subtractive self-aligned via and plug patterning for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate. The first layer includes a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The interconnect structure further includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating. The metal lines of the first grating are spaced apart from the metal lines of the second grating.

Abstract translation: 描述了用于后端（BEOL）互连的消减自对准通孔和插塞图案。 在一个示例中，用于集成电路的互连结构包括设置在基板上方的互连结构的第一层。 第一层包括在第一方向上交替的金属线和介质线的第一光栅。 介质线具有高于金属线的最上表面的最上表面。 互连结构还包括设置在互连结构的第一层上方的互连结构的第二层。 第二层包括垂直于第一方向的第二方向的交替金属线和介质线的第二光栅。 介质线具有低于金属线的最下表面的最下表面。 第二光栅的介质线与第一光栅的介质线重叠并接触，但不同。 第一光栅的金属线与第二光栅的金属线间隔开。

公开(公告)号：US20200091101A1

公开(公告)日：2020-03-19

申请号：US16692589

申请日：2019-11-22

Applicant: INTEL CORPORATION

Inventor： CHARLES H. WALLACE ,  HOSSAM A. ABDALLAH ,  ELLIOT N. TAN ,  SWAMINATHAN SIVAKUMAR ,  OLEG GOLONZKA ,  ROBERT M. BIGWOOD

IPC: H01L23/00 ,  G03F1/36 ,  H01L21/027 ,  G03F1/70 ,  G03F7/00 ,  G03F7/40 ,  G03F7/20 ,  H01L21/02 ,  H01L21/263 ,  H01L27/02 ,  G03F1/50 ,  G03F7/16 ,  H01L21/306 ,  H01L21/308

Abstract: Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may be arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern. The pattern decomposition techniques may be integrated into any number of patterning processes, such as litho-freeze-litho-etch and litho-etch-litho-etch patterning processes.

公开(公告)号：US20160190009A1

公开(公告)日：2016-06-30

申请号：US14911991

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： CHARLES H. WALLACE ,  PAUL A. NYHUS ,  ELLIOT N. TAN ,  SWAMINATHAN SIVAKUMAR

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L21/76883 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects are described. In an example, an interconnect structure for an integrated circuit includes a first layer disposed above a substrate. The first layer of the interconnect structure includes a grating of alternating metal lines and dielectric lines in a first direction. A second layer of the interconnect structure is disposed above the first layer. The second layer includes a grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. Each metal line of the grating of the second layer is disposed on a recessed dielectric line composed of alternating distinct regions of a first dielectric material and a second dielectric material corresponding to the alternating metal lines and dielectric lines of the first layer of the interconnect structure.

Abstract translation: 描述了用于后端（BEOL）互连的上一层自对准通孔和插图图案。 在一个示例中，用于集成电路的互连结构包括设置在基板上方的第一层。 互连结构的第一层包括在第一方向上交替的金属线和介质线的光栅。 互连结构的第二层设置在第一层上。 第二层包括垂直于第一方向的第二方向的交替金属线和介质线的光栅。 第二层的光栅的每个金属线设置在由互连结构的第一层的交替金属线和介电线对应的第一介电材料和第二介电材料的交替不同区域组成的凹陷介质线上。

公开(公告)号：US20210104459A1

公开(公告)日：2021-04-08

申请号：US16464565

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： BALIJEET S. BAINS ,  CHARLES H. WALLACE ,  ZHANPING CHEN

IPC: H01L23/525 ,  H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L23/532

Abstract: Embodiments herein describe techniques for fuse lines and plugs formation. A semiconductor device may include a fuse line having a nominal fuse segment abutted to a necked fuse segment. The nominal fuse segment may be wider than the necked fuse segment. A first spacer may be along a first side of the fuse line and a second spacer along a second side opposite to the first side of the fuse line. The first spacer may include a part having a width at least twice a width of a part of the second spacer. A plug within a vicinity of the necked fuse segment may have a plug width that may be at least twice a plug with of a plug of an interconnect line outside the vicinity. Other embodiments may also be described and claimed.

公开(公告)号：US20170139318A1

公开(公告)日：2017-05-18

申请号：US15419147

申请日：2017-01-30

Applicant: INTEL CORPORATION

Inventor： CHARLES H. WALLACE ,  HOSSAM M. ABDALLAH ,  ELLIOT N. TAN ,  SWAMINATHAN SIVAKUMAR ,  OLEG GOLONZKA ,  ROBERT M. BIGWOOD

IPC: G03F1/36 ,  G03F7/20 ,  G03F1/50 ,  H01L21/027 ,  H01L21/308

CPC classification number: H01L24/09 ,  G03F1/50 ,  G03F1/70 ,  G03F7/0035 ,  G03F7/16 ,  G03F7/40 ,  G03F7/70741 ,  H01L21/02345 ,  H01L21/0273 ,  H01L21/2633 ,  H01L21/30604 ,  H01L21/3086 ,  H01L27/0207 ,  H01L2224/0801 ,  H01L2224/08053 ,  H01L2224/0912 ,  H01L2924/14

Abstract: Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may be arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern. The pattern decomposition techniques may be integrated into any number of patterning processes, such as litho-freeze-litho-etch and litho-etch-litho-etch patterning processes.

公开(公告)号：US20160204002A1

公开(公告)日：2016-07-14

申请号：US14914095

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： CHARLES H. WALLACE ,  PAUL A. NYHUS

IPC: H01L21/48 ,  H01L21/764 ,  H01L23/498

CPC classification number: H01L21/486 ,  H01L21/4846 ,  H01L21/764 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Self-aligned via and plug patterning for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate. The first layer includes a grating of alternating metal lines and dielectric lines in a first direction. A second layer of the interconnect structure is disposed above the first layer. The second layer includes a grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. Each metal line of the grating of the second layer is disposed on a recessed dielectric line having alternating distinct regions of a first dielectric material and a second dielectric material corresponding to the alternating metal lines and dielectric lines of the first layer of the interconnect structure. Each dielectric line of the grating of the second structure has a continuous region of a third dielectric material distinct from the alternating distinct regions of the first dielectric material and the second dielectric material.

Abstract translation: 描述了用于后端（BEOL）互连的自对准通孔和插头图案。 在一个示例中，用于集成电路的互连结构包括设置在基板上方的互连结构的第一层。 第一层包括在第一方向上交替的金属线和介质线的光栅。 互连结构的第二层设置在第一层上。 第二层包括垂直于第一方向的第二方向的交替金属线和介质线的光栅。 第二层的光栅的每个金属线设置在具有与第一介电结构的第一层的交替金属线和介电线相对应的第一介电材料和第二介电材料的交替的不同区域的凹陷介质线上。 第二结构的光栅的每个介质线具有不同于第一介电材料和第二介电材料的交替不同区域的第三电介质材料的连续区域。