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    METHOD AND STRUCTURE TO CONTACT TIGHT PITCH CONDUCTIVE LAYERS WITH GUIDED VIAS
    6.
    发明申请
    METHOD AND STRUCTURE TO CONTACT TIGHT PITCH CONDUCTIVE LAYERS WITH GUIDED VIAS 有权
    方法和结构与指导VIAS接触导电层

    公开(公告)号：US20160148869A1

    公开(公告)日：2016-05-26

    申请号：US14905269

    申请日：2013-08-21

    Applicant: INTEL CORPORATION

    Inventor： Richard E. SCHENKER ,  Elliot N. TAN

    IPC: H01L23/522 ,  H01L21/02 ,  H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L23/528

    CPC classification number: H01L23/5226 ,  H01L21/02115 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76804 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An apparatus including a circuit substrate; a first interconnect layer in a first plane on the substrate and a second interconnect layer in a different second plane on the substrate; and a hardmask layer separating the first interconnect layer and the second interconnect layer, wherein the hardmask layer comprises alternating guide sections comprising different hard mask materials, and a via guide. A method including forming a dielectric layer on an integrated circuit structure; forming a first interconnect layer having interconnect lines in the dielectric layer; forming a hardmask layer on a surface of the dielectric layer, the hardmask layer comprising alternating hardmask materials which form guide sections over the interconnect lines; forming a via guide in one of the guide sections; and forming a second interconnect layer over the hardmask guide layer which is electrically connected to one of the interconnect lines through the via guide.

    Abstract translation: 一种包括电路基板的设备; 在所述衬底上的第一平面中的第一互连层和在所述衬底上的不同第二平面中的第二互连层; 以及分离所述第一互连层和所述第二互连层的硬掩模层，其中所述硬掩模层包括包括不同硬掩模材料的交替引导部分和通孔引导件。 一种包括在集成电路结构上形成介电层的方法; 在介电层中形成具有互连线的第一互连层; 在所述电介质层的表面上形成硬掩模层，所述硬掩模层包括交替的硬掩模材料，所述硬掩模材料在所述互连线上形成引导部分; 在一个引导部分中形成通孔引导件; 以及在所述硬掩模引导层上形成第二互连层，所述第二互连层通过所述通孔引导件电连接到所述互连线之一。

    VERTICAL EDGE BLOCKING (VEB) TECHNIQUE FOR INCREASING PATTERNING PROCESS MARGIN
    8.
    发明公开
    VERTICAL EDGE BLOCKING (VEB) TECHNIQUE FOR INCREASING PATTERNING PROCESS MARGIN 审中-公开

    公开(公告)号：US20230145089A1

    公开(公告)日：2023-05-11

    申请号：US18096351

    申请日：2023-01-12

    Applicant: Intel Corporation

    Inventor： Leonard P. GULER ,  Chul-Hyun LIM ,  Paul A. NYHUS ,  Elliot N. TAN ,  Charles H. WALLACE

    IPC: H01L21/768 ,  H01L21/311 ,  H01L29/423 ,  H01L29/417

    CPC classification number: H01L21/76816 ,  H01L21/31144 ,  H01L29/42316 ,  H01L29/41725 ,  H01L21/76877

    Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such semiconductor devices. In an embodiment, a method of fabricating a semiconductor device comprises, forming a first grating of parallel first lines, forming a second grating of parallel second lines, wherein the second lines are substantially orthogonal to the first lines, and wherein the first lines and second lines define a plurality of first openings, disposing a conformal mask layer over the first lines and the second lines, wherein the conformal mask layer partially fills the first openings and defines a second opening within each of the first openings, disposing a hardmask over the conformal mask layer, wherein the hardmask fills the second openings, patterning third openings into the hardmask, wherein the third openings clear the hardmask from at least one of the second openings, and removing the mask layer proximate to cleared second openings to clear first openings.

    PATTERN DECOMPOSITION LITHOGRAPHY TECHNIQUES
    9.
    发明申请
    PATTERN DECOMPOSITION LITHOGRAPHY TECHNIQUES 有权

    公开(公告)号：US20210375807A1

    公开(公告)日：2021-12-02

    申请号：US17404870

    申请日：2021-08-17

    Applicant: Intel Corporation

    Inventor： Charles H. WALLACE ,  Hossam A. ABDALLAH ,  Elliot N. TAN ,  Swaminathan SIVAKUMAR ,  Oleg GOLONZKA ,  Robert M. BIGWOOD

    IPC: H01L23/00 ,  G03F7/00 ,  G03F7/40 ,  H01L21/027 ,  G03F1/36 ,  G03F1/70 ,  G03F7/20 ,  H01L21/02 ,  H01L21/263 ,  H01L27/02 ,  G03F1/50 ,  G03F7/16 ,  H01L21/306 ,  H01L21/308

    Abstract: Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may be arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern. The pattern decomposition techniques may be integrated into any number of patterning processes, such as litho-freeze-litho-etch and litho-etch-litho-etch patterning processes.

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