公开(公告)号：US10045735B2

公开(公告)日：2018-08-14

申请号：US14499100

申请日：2014-09-27

Applicant: Intel Corporation

Inventor： Nicholas P. Cowley ,  Ruchir Saraswat ,  Richard J. Goldman

IPC: A61B5/05 ,  A61B5/00 ,  H04B13/00 ,  G16H40/63 ,  H04W4/38 ,  H04W4/80 ,  A61B5/053 ,  H04L29/08

Abstract: Technologies for the sensing of biofeedback signals of a user include a body area network (BAN) system comprising one or more biofeedback sensors and one or more BAN controllers. The biofeedback sensors are configured to sense BAN signals, which may include biofeedback signals and body-coupled communication (BCC) signals. To facilitate communication, the biofeedback sensors may demultiplex the sensed BAN signals into biofeedback signals and incoming BCC signals. Similarly, the biofeedback sensors may multiplex outgoing BCC signals with sensed biofeedback signals. The BAN controller may communicate in a similar manner. Additionally, the BAN controller may process incoming BCC signals and provide feedback to the user based on BCC signals received from the biofeedback sensors.

公开(公告)号：US09882472B2

公开(公告)日：2018-01-30

申请号：US14496838

申请日：2014-09-25

Applicant: Intel Corporation

Inventor： Nicholas P. Cowley ,  Ruchir Saraswat ,  Richard J. Goldman ,  David T. Bernard ,  Gordon J. Walsh ,  Michael Langan

IPC: G05F1/56 ,  H02M3/156 ,  H02M1/36 ,  H02M1/00

CPC classification number: H02M3/156 ,  G05F1/56 ,  H02M1/36 ,  H02M2001/0032 ,  H02M2001/009 ,  H02M2003/1566

Abstract: In at least one embodiment there is provided a method for managing bulk capacitance of a power supply system. The method includes precharging first and second bulk capacitors of the power supply system to approximately a first output voltage level and a second output voltage level, respectively; receiving a first command signal to generate, by the power supply, the first output voltage level; coupling the first bulk capacitance to load circuitry coupled to the power supply; receiving a second command signal to generate, by the power supply, the second output voltage level; and coupling the second bulk capacitance to the load circuitry coupled to the power supply.

公开(公告)号：US20160180679A1

公开(公告)日：2016-06-23

申请号：US14580727

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： Nicholas P. Cowley ,  Ruchir Saraswat ,  Colin L. Perry ,  Matthew T. Aitken ,  Richard J. Goldman ,  Chi Man Kan

IPC: G08B21/02 ,  G08B3/10 ,  G08B5/36

CPC classification number: G08B21/02 ,  G06Q50/12 ,  G06Q50/22 ,  G08B3/10 ,  G08B5/36

Abstract: A method monitors the consumption of materials, including determining the presence of materials in a smart receptacle using a sensor located in the smart receptacle. A server is alerted when an actionable item is detected.

Abstract translation: 一种方法监测材料的消耗，包括使用位于智能插座中的传感器确定智能插座中材料的存在。 当检测到可操作的项目时，将提醒服务器。

公开(公告)号：US09287196B2

公开(公告)日：2016-03-15

申请号：US13730331

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Ruchir Saraswat ,  Uwe Zillmann ,  Andre Schaefer ,  Tor Lund-Larsen

IPC: H01L27/08 ,  H01L23/48 ,  H01L23/522 ,  H01L25/065 ,  H01L27/06 ,  H01L23/64

CPC classification number: H01L23/481 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/642 ,  H01L23/645 ,  H01L25/0657 ,  H01L27/0688 ,  H01L2223/6616 ,  H01L2223/6666 ,  H01L2223/6672 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Resonant clocking for three-dimensional stacked devices. An embodiment of an apparatus includes a stack including integrated circuit dies; and through silicon vias through at least one of the dies, wherein at least a first through silicon via of the through silicon vias includes a capacitive structure or an inductive structure, the first through silicon via being formed in a first die of the plurality of dies. The apparatus includes a resonant circuit, the first through silicon via used as a first circuit element of the resonant circuit.

Abstract translation: 谐振时钟三维堆叠器件。 装置的实施例包括：堆叠，其包括集成电路管芯; 并且通过至少一个管芯的硅通孔，其中穿过硅通孔的至少第一通孔硅通道包括电容结构或电感结构，所述第一穿硅通孔形成在所述多个管芯的第一管芯中 。 该装置包括谐振电路，第一通孔硅用作谐振电路的第一电路元件。

公开(公告)号：US11037896B2

公开(公告)日：2021-06-15

申请号：US16216881

申请日：2018-12-11

Applicant: Intel Corporation

Inventor： Kevin J. Lee ,  Ruchir Saraswat ,  Uwe Zillmann ,  Nicholas P. Cowley ,  Richard J. Goldman

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/66 ,  G06F1/16 ,  H01F27/28 ,  H01L23/64 ,  H03H7/42 ,  H03H9/64 ,  H01L23/525

Abstract: Described is an apparatus which comprises: a backside of a first die having a redistribution layer (RDL); and one or more passive planar devices disposed on the backside, the one or more passive planar devices formed in the RDL.

公开(公告)号：US10683189B2

公开(公告)日：2020-06-16

申请号：US15190848

申请日：2016-06-23

Applicant: Intel Corporation

Inventor： Ruchir Saraswat ,  Nicholas P. Cowley ,  Richard J. Goldman

IPC: B66B1/18 ,  B66B1/28 ,  B66B1/34

Abstract: Processes, apparatuses, and systems associated with usage and contextual-based elevator operations management that have the capability to learn and to constantly adapt to usage patterns on a temporal basis through continuous monitoring of elevator journeys. An elevator journey may include a start and termination floor for an individual. Elevator journey data may be used to predict patterns of usage and maybe used, for example, to optimize the number of elevators operational at any time, determine the optimal parking position of each elevator, and/or determine an efficient allocation of elevators to groups or related floors.

公开(公告)号：US10455308B2

公开(公告)日：2019-10-22

申请号：US15502495

申请日：2014-09-17

Applicant: Intel Corporation

Inventor： Kevin J. Lee ,  Ruchir Saraswat ,  Uwe Zillmann ,  Valluri Bob Rao ,  Tor Lund-Larsen ,  Nicholas P. Cowley

IPC: H04R19/04 ,  H04R1/04 ,  B81B7/02 ,  H01L23/00 ,  H01L21/683 ,  H01L23/48 ,  B81C1/00 ,  H01L21/768 ,  H04R1/40 ,  H04R19/00

Abstract: Embodiments of the present disclosure describe a die with integrated microphone device using through-silicon vias (TSVs) and associated techniques and configurations. In one embodiment, an apparatus includes an apparatus comprising a semiconductor substrate having a first side and a second side disposed opposite to the first side, an interconnect layer formed on the first side of the semiconductor substrate, a through-silicon via (TSV) formed through the semiconductor substrate and configured to route electrical signals between the first side of the semiconductor substrate and the second side of the semiconductor substrate, and a microphone device formed on the second side of the semiconductor substrate and electrically coupled with the TSV. Other embodiments may be described and/or claimed.

公开(公告)号：US10070816B2

公开(公告)日：2018-09-11

申请号：US14481375

申请日：2014-09-09

Applicant: Intel Corporation

Inventor： Nicholas P. Cowley ,  Ruchir Saraswat ,  Richard J. Goldman

IPC: A61B5/00 ,  A61B5/103 ,  A43B3/00 ,  A61B5/11

CPC classification number: A61B5/6807 ,  A43B3/0005 ,  A43B17/00 ,  A61B5/1038 ,  A61B5/112 ,  A61B2560/0214 ,  A61B2562/0247 ,  A61B2562/028 ,  A61B2562/12 ,  A61B2562/164 ,  A61B2562/166 ,  A61B2562/187

Abstract: Embodiments of the present disclosure provide techniques and configurations for an orthotic device. In one instance, the device may include an orthotic device body and at least two sensors spatially disposed inside the orthotic device body. A first sensor may provide a first output responsive to pressure resulting from application of mechanical force to the orthotic device body. A second sensor may provide a second output responsive to flexing resulting from the application of mechanical force to the orthotic device body. The device may also include a control unit communicatively coupled with the sensors to receive and process the outputs provided by the sensors in response to pressure and flexing. Other embodiments may be described and/or claimed.

公开(公告)号：US09921640B2

公开(公告)日：2018-03-20

申请号：US13631092

申请日：2012-09-28

Applicant: INTEL CORPORATION

Inventor： Uwe Zillmann ,  Andre Schaefer ,  Ruchir Saraswat ,  Telesphor Kamgaing ,  Paul B. Fischer ,  Guido Droege

IPC: H01L23/48 ,  G06F1/32 ,  H05K1/02 ,  H05K1/16

CPC classification number: G06F1/3296 ,  H01L2924/0002 ,  H05K1/0262 ,  H05K1/165 ,  Y02D10/172 ,  Y10T29/4913 ,  H01L2924/00

Abstract: Magnetically enhanced inductors integrated with microelectronic devices at chip-level. In embodiments, magnetically enhanced inductors include a through substrate vias (TSVs) with fill metal to carry an electrical current proximate to a magnetic layer disposed on a substrate through which the TSV passes. In certain magnetically enhanced inductor embodiments, a TSV fill metal is disposed within a magnetic material lining the TSV. In certain magnetically enhanced inductor embodiments, a magnetically enhanced inductor includes a plurality of interconnected TSVs disposed proximate to a magnetic material layer on a side of a substrate. In embodiments, voltage regulation circuitry disposed on a first side of a substrate is integrated with one or more magnetically enhanced inductors utilizing a TSV passing through the substrate. In further embodiments, integrated circuitry on a same substrate as the magnetically enhanced inductor, or on another substrate stacked thereon, completes the VR and/or is powered by the VR circuitry.

公开(公告)号：US09911689B2

公开(公告)日：2018-03-06

申请号：US15038623

申请日：2013-12-23

Applicant: INTEL CORPORATION

Inventor： Kevin J. Lee ,  Ruchir Saraswat ,  Uwe Zillmann ,  Nicholas P. Cowley ,  Andre Schaefer ,  Rinkle Jain ,  Guido Droege

IPC: H01L21/48 ,  H01L23/522 ,  H01L21/768 ,  H01L49/02 ,  H01L25/065 ,  H01L23/48 ,  H01L21/822 ,  H01L23/492 ,  H01L23/498 ,  H01L27/06

CPC classification number: H01L23/5223 ,  H01L21/4846 ,  H01L21/486 ,  H01L21/4875 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/481 ,  H01L23/492 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L25/0657 ,  H01L27/0629 ,  H01L28/90 ,  H01L2225/06544 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques are disclosed for forming a through-body-via (TBV) isolated coaxial capacitor in a semiconductor die. In some embodiments, a cylindrical capacitor provided using the disclosed techniques may include, for example, a conductive TBV surrounded by a dielectric material and an outer conductor plate. The TBV and outer plate can be formed, for example, so as to be self-aligned with one another in a coaxial arrangement, in accordance with some embodiments. The disclosed capacitor may extend through the body of a host die such that its terminals are accessible on the upper and/or lower surfaces thereof. Thus, in some cases, the host die can be electrically connected with another die to provide a die stack or other three-dimensional integrated circuit (3D IC), in accordance with some embodiments. In some instances, the disclosed capacitor can be utilized, for example, to provide integrated capacitance in a switched-capacitor voltage regulator (SCVR).